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| author | Ed Tsai <ed.tsai@mediatek.com> | 2026-03-10 08:52:28 +0800 |
|---|---|---|
| committer | Martin K. Petersen <martin.petersen@oracle.com> | 2026-03-10 21:34:59 -0400 |
| commit | 6ab94d0194ddca662da69cf42b98dcf74690ed92 (patch) | |
| tree | 33dfbecd2dc0a3a55270504b7ffaf66794af1f43 /tools/lib/python | |
| parent | 096cd6b7adf21791827a045d464242d93a6fd54e (diff) | |
scsi: ufs: core: Add quirks for VCC ramp-up delay
On some platforms, the VCC regulator has a slow ramp-up time. Add a delay
after enabling VCC to ensure voltage has fully stabilized before we enable
the clocks.
Reviewed-by: Bart Van Assche <bvanassche@acm.org>
Signed-off-by: Ed Tsai <ed.tsai@mediatek.com>
Link: https://patch.msgid.link/20260310005230.4001904-4-ed.tsai@mediatek.com
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'tools/lib/python')
0 files changed, 0 insertions, 0 deletions