Merge tag 'zynqmp-dt-for-7.3' of https://github.com/Xilinx/linux-xlnx into soc/dt

arm64: Xilinx DT changes for 7.3

bindings:
- Cleanup xilinx.txt
- Update ZynqMP firmware and clock descriptions

zynq:
- Drop bias-high-impedance on SD

zynqmp:
- Drop bias-high-impedance on SD
- Correct indentation

versalnet:
- Enable firmware interface including clock, power and reset

* tag 'zynqmp-dt-for-7.3' of https://github.com/Xilinx/linux-xlnx:
  arm64: versal-net: Switch Versal NET to firmware clock interface
  dt-bindings: clock: versal-clk: Fix Versal NET clock validation
  dt-bindings: clock: Move xlnx,zynqmp-clk to its own schema
  dt-bindings: clock: versal-clk: Fix mio_clk index range in clock-names pattern
  dt-bindings: firmware: xilinx: Add missing example for ZynqMP
  dt-bindings: xilinx: Remove EDK/Ethernet references
  arm64: dts: xilinx: zynqmp-sck: Correct indentation
  arm: dts: xilinx: drop bias-high-impedance on SDIO CD/WP pins
  arm64: dts: xilinx: drop bias-high-impedance on SDIO CD/WP pins

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

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