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authorAbel Vesa <abel.vesa@linaro.org>2024-12-12 18:50:39 +0200
committerBjorn Andersson <andersson@kernel.org>2024-12-20 21:52:23 -0600
commitffb21c1e19b17f3b2f5f56c70e379ef7c96afad5 (patch)
treed78e2f519b5b7bb887e45eb24543937ab846f62f /tools/lib/python/kdoc/python_version.py
parent89fc83a9472812052610970b41fd44de94224b32 (diff)
arm64: dts: qcom: x1e80100: Describe the SDHC controllers
The X Elite platform features two SDHC v5 controllers. Describe the controllers along with the pin configuration in TLMM for the SDC2, since they are hardwired and cannot be muxed to any other function. The SDC4 pin configuration can be muxed to different functions, so leave those to board specific dts. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20241212-x1e80100-qcp-sdhc-v4-1-a74c48ee68a3@linaro.org [bjorn: Replaced 0s with QCOM_ICC_TAG_ALWAYS] Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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