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| author | Shawn Lin <shawn.lin@rock-chips.com> | 2026-03-06 20:20:41 +0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2026-03-10 09:34:27 +0100 |
| commit | 41b1a6760959017c4fa1dbc7c3cc318406ab1455 (patch) | |
| tree | 8ed12d1ce57d7b3b1e6a51f9b84024f731959c21 /tools/lib/python/feat/parse_features.py | |
| parent | 3e65e426d4575a66a82928eb41b6d83f36e5ce9c (diff) | |
clk: rockchip: rk3568: Add PCIe pipe clock gates
The PCIe pipe clocks are currently left as orphan clocks and remain
enabled indefinitely, which is suboptimal. Add the missing clock gates
so the PCIe driver can explicitly manage them when not in use. In order
not to break compatibility with old DTB, mark them as CLK_IGNORE_UNUSED.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Link: https://patch.msgid.link/1772799641-32164-1-git-send-email-shawn.lin@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'tools/lib/python/feat/parse_features.py')
0 files changed, 0 insertions, 0 deletions