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authorMiquel Raynal <miquel.raynal@bootlin.com>2026-05-26 16:56:52 +0200
committerPratyush Yadav <pratyush@kernel.org>2026-05-27 14:36:03 +0200
commit48007986232858f94fc1ba2af4b360008e3e146b (patch)
treeabec0ebb4bfd193fca962dacdf55191d0b2139d1 /scripts/patch-kernel
parenteb403cb56e13d7efd742511c1a92b89dc9db8658 (diff)
mtd: spi-nor: winbond: Add W25Q02NWxxIM CMP locking support
This chip has support for the locking complement (CMP) feature. Add the relevant bit to enable it. Unfortunately, this chip also comes with an incorrect BFPT table, indicating the Control Register cannot be read back. This is wrong, reading back the register works and has no (observed) side effect. The datasheet clearly indicates supporting the 35h command and all bits from the CR are marked readable. QE and CMP bits are inside, and can be properly read back. Add a fixup for this, otherwise it would defeat the use of the CMP feature. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Pratyush Yadav <pratyush@kernel.org>
Diffstat (limited to 'scripts/patch-kernel')
0 files changed, 0 insertions, 0 deletions