diff options
| author | Mark Rutland <mark.rutland@arm.com> | 2026-06-03 12:06:12 +0100 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2026-06-03 16:50:47 +0100 |
| commit | 247bd153905085c18ff9006cca1ccb96dfd18e7f (patch) | |
| tree | df6c454bc500110ff9941d20dc74a2298dd6b976 /scripts/decode_stacktrace.sh | |
| parent | ae24f6b06e90681ec36b9c21c3f5c09618350f5a (diff) | |
arm64: fpsimd: Fix type mismatch in sme_{save,load}_state()
The sme_save_state() and sme_load_state() functions take a 32-bit int
argument that describes whether to save/restore ZT0. Their assembly
implementations consume the entire 64-bit register containing this
32-bit value, and will attempt to save/restore ZT0 if any bit of
that 64-bit register is non-zero.
Per the AAPCS64 parameter passing rules, the callee is responsible for
any necessary widening, and the upper 32-bits are permitted to contain
arbitrary values. If the upper 32 bits are non-zero, this could result
in an unexpected attempt to save/restore ZT0, and consequently could
lead to unexpected traps/undefs/faults.
In practice compilers are very unlikely to generate code where the upper
32-bits would be non-zero, but they are permitted to do so.
Fix this by only consuming the low 32 bits of the register, and update
comments accordingly.
Fixes: 95fcec713259 ("arm64/sme: Implement context switching for ZT0")
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Fuad Tabba <tabba@google.com>
Cc: James Morse <james.morse@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Oliver Upton <oupton@kernel.org>
Cc: Vladimir Murzin <vladimir.murzin@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: stable@vger.kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'scripts/decode_stacktrace.sh')
0 files changed, 0 insertions, 0 deletions
