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| author | Dapeng Mi <dapeng1.mi@linux.intel.com> | 2026-05-15 14:11:38 +0800 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2026-05-19 13:49:04 +0200 |
| commit | 331c3e4fa39a87560c09bdd878652090ae040b69 (patch) | |
| tree | d2095d540bff8820abe22e5ce65a15244c5ce752 /rust/kernel | |
| parent | e99fb45436eaa4ac1b72a8e4af56381f59759b0c (diff) | |
perf/x86/intel: Update event constraints and cache_extra_regsfor LNL
Update perf hard-coded event constraints and cache_extra_regs[] for
Lunarlake according to the latest LNL perfmon events (V1.22).
LNL introduces new extra register values for the OCR L3 cache events,
so introduce lnc_hw_cache_extra_regs[] and skt_hw_cache_extra_regs[] to
reflect the changes.
LNL perfmon events:
https://github.com/intel/perfmon/blob/main/LNL/events/lunarlake_lioncove_core.json
https://github.com/intel/perfmon/blob/main/LNL/events/lunarlake_skymont_core.json
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260515061143.338553-7-dapeng1.mi@linux.intel.com
Diffstat (limited to 'rust/kernel')
0 files changed, 0 insertions, 0 deletions