diff options
| author | Dapeng Mi <dapeng1.mi@linux.intel.com> | 2026-04-30 08:25:58 +0800 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2026-05-05 12:47:24 +0200 |
| commit | 5c3cdc74af25fc7f64a3ed260b4f6eb8313a3b75 (patch) | |
| tree | 10e415117cec84d1b004e087ded4a21fa8531c06 /rust/kernel/alloc | |
| parent | aa4384bc8f4360167f3c3d5322121fe892289ea2 (diff) | |
perf/x86/intel: Consolidate MSR_IA32_PERF_CFG_C tracking
Both Auto Counter Reload (ACR) and Architectural PEBS use the PERF_CFG_C
MSRs to configure event behavior. Currently, the driver maintains two
independent variables acr_cfg_c and cfg_c_val to cache the values intended
for these MSRs.
Using separate variables to track a single hardware register state is
error-prone and can lead to configuration conflicts. Consolidate the
tracking into a single cfg_c_val variable to ensure a unified and
consistent view of the PERF_CFG_C MSR state.
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260430002558.712334-6-dapeng1.mi@linux.intel.com
Diffstat (limited to 'rust/kernel/alloc')
0 files changed, 0 insertions, 0 deletions