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| author | Dapeng Mi <dapeng1.mi@linux.intel.com> | 2026-05-15 14:11:34 +0800 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2026-05-19 13:49:02 +0200 |
| commit | 30d82ddee085b4b0f9a1b5bded53acaca68d9a52 (patch) | |
| tree | 1ac03340f47174653319a6d9439ee0a5f47aae18 /rust/kernel/alloc/allocator.rs | |
| parent | acc41cdcb091453f48381d1c0d2e76b63c9d985f (diff) | |
perf/x86/intel: Update event constraints and cache_extra_regsfor SPR
Update perf hard-coded event constraints and cache_extra_regs[] for
Sapphire rapids according to the latest SPR perfmon events (v1.39).
Emerald Rapids (EMR) and Granite Rapids (GNR) share exactly same event
constraints and extra MSR values with SPR. No extra changes are needed
for EMR and GNR.
Please note the change could temporarily impact other platforms which
share the hard coded data structures, but it would be fixed in
subsequent patches soon.
SPR perfmon events:
https://github.com/intel/perfmon/blob/main/SPR/events/sapphirerapids_core.json
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260515061143.338553-3-dapeng1.mi@linux.intel.com
Diffstat (limited to 'rust/kernel/alloc/allocator.rs')
0 files changed, 0 insertions, 0 deletions