diff options
| author | Dave Jiang <dave.jiang@intel.com> | 2026-01-14 12:20:28 -0600 |
|---|---|---|
| committer | Dave Jiang <dave.jiang@intel.com> | 2026-01-22 14:58:03 -0700 |
| commit | 7ff8b1d60881c5f97b5ae426e14d2822917d3b69 (patch) | |
| tree | 4881244399a0d6e70d045cd5a823453c3b6c30fb /rust/alloc/collections/git@git.tavy.me:linux.git | |
| parent | bcfa289932a703dd189466ea5947212e8dddd399 (diff) | |
cxl/pci: Remove CXL VH handling in CONFIG_PCIEAER_CXL conditional blocks from core/pci.c
Create new config CONFIG_CXL_RAS and put all CXL RAS items behind the
config. The config will depend on CPER and PCIE AER to build. Move the
related VH RAS code from core/pci.c to core/ras.c.
Restricted CXL host (RCH) RAS functions will be moved in a future patch.
Cc: Robert Richter <rrichter@amd.com>
Reviewed-by: Joshua Hahn <joshua.hahnjy@gmail.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Co-developed-by: Terry Bowman <terry.bowman@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Link: https://patch.msgid.link/20260114182055.46029-8-terry.bowman@amd.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Diffstat (limited to 'rust/alloc/collections/git@git.tavy.me:linux.git')
0 files changed, 0 insertions, 0 deletions
