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authorBiju Das <biju.das.jz@bp.renesas.com>2025-11-29 16:43:13 +0000
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2025-12-17 15:07:07 +0100
commit42eeed6d9f31e6063bf98d71212a6de3aac8cdd3 (patch)
tree16922af55177d45929eb53b188aa272cac4268fe /rust/alloc/collections/git@git.tavy.me:linux.git
parent068b862f5025920e3e10228e9904c2560e08b855 (diff)
serial: sh-sci: Add support for RZ/G3E RSCI
Add support for RZ/G3E RSCI. RSCI IP found on the RZ/G3E SoC is similar to RZ/T2H, but it has a 32-stage FIFO. It has 6 clocks(5 module clocks + 1 external clock) instead of 3 clocks(2 module clocks + 1 external clock) on T2H, has 6 irqs compared to 4 on RZ/T2H and has multiple resets. Add support for the hardware flow control. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://patch.msgid.link/20251129164325.209213-18-biju.das.jz@bp.renesas.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'rust/alloc/collections/git@git.tavy.me:linux.git')
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