diff options
| author | Sen Wang <sen@ti.com> | 2026-06-16 18:33:22 -0500 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2026-06-17 14:56:31 +0100 |
| commit | fdf043f5f3bae150b678feae3d7bb1beed87ec14 (patch) | |
| tree | 43aba14e740d62a376c76a1db892beef8f5a2868 /mm/tests/git@git.tavy.me:linux.git | |
| parent | 1a3c8e28959790ae3e06029681418278b7821a3c (diff) | |
ASoC: tlv320aic3x: restrict CLKDIV bypass Q values in dual-rate mode
The datasheet documents that when the PLL is disabled and dual-rate mode
is enabled, only Q values {4, 8, 9, 12, 16} are valid for the CLKDIV
bypass path; all other Q values produce invalid bitclock output.
The existing loop iterates Q from 2 to 17 without this restriction,
causing silent audio failure when an out-of-spec Q is picked.
Restrict the Q search to the allowed set in dual-rate mode.
Fixes: 4f9c16ccfa26 ("[ALSA] soc - tlv320aic3x - revisit clock setup")
Suggested-by: Mir Jeffres <m-jeffres@ti.com>
Signed-off-by: Sen Wang <sen@ti.com>
Link: https://patch.msgid.link/20260616233322.873081-1-sen@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'mm/tests/git@git.tavy.me:linux.git')
0 files changed, 0 insertions, 0 deletions