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| author | Matt Roper <matthew.d.roper@intel.com> | 2025-10-13 13:09:52 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2025-10-14 07:44:57 -0700 |
| commit | 082547d8b401f8eef076d18344c267fe1bddb055 (patch) | |
| tree | 64dbc5bca318203312b9b99cfb002b99fbe02953 /kernel/module/git@git.tavy.me:linux.git | |
| parent | 9c52402f6bd0b82f150236bb9b5895af00bb1188 (diff) | |
drm/xe: Skip L2 / TDF cache flushes if primary GT is disabled
If the primary GT is disabled via configfs, GT-side L2 and TD cache
flushes are unnecessary since nothing is using/filling these caches.
Reviewed-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Link: https://lore.kernel.org/r/20251013200944.2499947-34-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Diffstat (limited to 'kernel/module/git@git.tavy.me:linux.git')
0 files changed, 0 insertions, 0 deletions