diff options
| author | Daniele Briguglio <hello@superkali.me> | 2026-04-19 13:43:09 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2026-04-27 13:32:29 +0200 |
| commit | 06c990bffdbea7cf655e728f4423ecd13fb030f6 (patch) | |
| tree | ad6793a9982d44c8d488b899346abc64ba099a3b /include | |
| parent | 254f49634ee16a731174d2ae34bc50bd5f45e731 (diff) | |
soc: rockchip: rk3588: add SYS_GRF SOC_CON6 register offset
Add the RK3588_SYSGRF_SOC_CON6 register offset to the RK3588 GRF
header. This register contains the I2S MCLK output to IO gate bits,
needed by the clock driver.
Signed-off-by: Daniele Briguglio <hello@superkali.me>
Reviewed-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://patch.msgid.link/20260419-rk3588-mclk-gate-grf-v4-4-513a42dd1dcc@superkali.me
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'include')
| -rw-r--r-- | include/soc/rockchip/rk3588_grf.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/soc/rockchip/rk3588_grf.h b/include/soc/rockchip/rk3588_grf.h index 02a7b2432d99..db0092fc66ad 100644 --- a/include/soc/rockchip/rk3588_grf.h +++ b/include/soc/rockchip/rk3588_grf.h @@ -19,4 +19,6 @@ /* Whether the LPDDR5 is in 2:1 (= 0) or 4:1 (= 1) CKR a.k.a. DQS mode */ #define RK3588_PMUGRF_OS_REG6_LP5_CKR BIT(0) +#define RK3588_SYSGRF_SOC_CON6 0x0318 + #endif /* __SOC_RK3588_GRF_H */ |