Merge tag 'drm-next-2026-08-20' of https://gitlab.freedesktop.org/drm/kernel

Pull drm updates from Dave Airlie:
 "Highlights:

   - dmemcg eviction support is good for low VRAM things like Steam
     Machine

   - AMD adds gfx6-8 modifier support for older GPUs that enables a
     bunch of wayland stuff

   - i915/xe has some new hw support but also a lot of display
     refactoring

  Everything:

  perf:
   - export perf_allow_ APIs for xe

  udmabuf:
   - remove default size limit of 64MB

  rust:
   - i/o rework (signed tag from driver-core tree)
   - add registration guard and registration data
   - fix unbounded lifetimes in ioctl handler args
   - fix a drm_dev_register race
   - gem_shmem: add DmaResvGuard helper
   - gpuvm: require send/sync for driver data
       - implement send/sync for GpuVaAlloc and GpuVmBo
       - add SmContext lifetime
   - rename dma_handle to dma_address
   - change pci_sriov_get_totalvfs return to unsigned int

  core:
   - create drm_of_get_panel_orientation
   - send per-connector hotplug events
   - add thunderbolt UBHR tunneling support

  connector:
   - add color format property

  dmem:
   - introduce a peak file
   - accept one region per limit
   - add dmemcg support for eviction

  gpusvm:
   - reorg code to give drivers more flexibility

  atomic:
   - add create_state callback and helper
   - add documentation on atomic commit lifetime

  buddy:
   - add per-order free
   - add used block scoreboard
   - fix UAF
   - test buffer clearance on resume
   - add phys_addr->block helper

  gem:
   - drop DRIVER_GEM_GPUVA flag

  ttm:
   - be more aggressive allocating below protection limit

  sched:
   - add test suite for concurrent job submissions

  hdmi:
   - hook the color format property in helpers

  mipi-dsi:
   - add MIPI_DSI_MODE_DSC_ALL_SLICES_IN_PKT

  bridge:
   - add atomic create callbacks
   - drop atomic reset
   - display-connector: don't autoenable HPD IRQ
   - trigger initial HPD for DP
   - ti-sn65dsi83: remove NO_HFP and NO_HBP mode flags
   - analogix_dp: switch to DP link training helpers

  dp:
   - add support for DSC max delta BPP

  edid:
   - parse panel type from DisplayID 2.x Display Parameters

  sysfb:
   - improve panel, stride, framebuffer size validation

  panel:
   - implement ref counting for struct drm_panel
   - himax-hx83121a: add backlight regulator support
   - novatek-nt36672a: Inline panel init sequences
   - visionox-vtdr6130: enable DSC
   - novatek-nt37801: Use mipi_dsi_*_multi() functions
   - samsung-s6d16d0: Fix prepare error handling
   - support Novatek NT36536 plus DT bindings
   - sofef00: fix backlight updates
   - osd101t2587: use mipi_dsi_*_multi interface
   - panel-edp: adjust timing for AUO displays
   - panel-lvds: support Opto Logic SCX1001511GGC49
   - panel-simple: support Kyocera tcg070wvlq
   - panel-edp: quirks
       - AUO B116XAT04.3, CMN N116BCP-EA2, CSW MNB601LS1-8
       - BOE NV116WH2-M30, BOE NT116WHM-N21, BOE NV116FH1-M31
       - BOE NV116FH1-M30, NV140FHM-N5B, TM156VDXP25
       - BOE NE160QDM-NY1, MB116AS01
   - new:
       - Samsung ATNA40HQ08-0, Anbernic TD4310
       - Chipone ICNA35XX, Ilitek ILI9488
       - Ilitek ILI7807S, Renesas R63419
       - MNE001BS6-2, MNF601BS4-1, Sharp LQ120P1JX51

  virtio:
   - add support for save/restore virtio_gpu_objects
   - abort vq wait on device removal

  amdgpu:
   - add color format DRM property
   - initial compute pipe reset support
   - add GFX 6-8 modifier support
   - initial DCN 6.0.0 support
   - dmemcg eviction support
   - improved boundary checking for bios parsing
   - RAS updates and rework
   - VCN secure submission fixes
   - 8K panel fix
   - Display KUNIT tests
   - parse panel type from DisplayID
   - Align IP discovery to pci device lifetime
   - SOC15 register macro cleanups
   - UVD memory placement fixes
   - GFX9 mode2 reset fixes
   - drop unnecessary BUG/BUG_ON
   - GFX8 soft reset rework
   - enable soft reset on GFX8
   - PSP/SMU 15.0.9 update
   - VI ASPM fix
   - userq fixes
   - amdgpu_vm_get_task_info_pasid lifetime fix
   - DC CACP support
   - change system_unbound_wq with system_dfl_wq
   - Loosen VFCT bios parsing to deal with pci=realloc
   - SI/SMU7 AC/DC switch fix
   - VM fence handling fix
   - GEM close optimisation
   - Apple Studio Display fixes
   - DC FRL fixes

  amdkfd:
   - initial compute pipe reset support
   - allow applications to opt out of sigbus on fatal errors
   - improve CRIU boundary checks
   - MQD handling rework
   - move TBA/TMA from system to device memory
   - avoid topology-lock in kfd_mmap
   - SVM eviction fixes

  radeon:
   - fix unset CONFIG_ACPI build

  i915:
   - Novalake (NVL display version 35) timing generator enabling
   - NVL DC3CO enabling
   - enable UBHR link rates on thunderbolt tunnels
   - Reduce Xe3+ PM demand peak bandwidth
   - enable pipe DMC error interrupts for display 30+
   - add kunit tests for DP link config selection
   - refactor and document DP link recovery
   - i915/xe driver display probe/remove/suspend/resume/shutdown cleanup
     and unification
   - i915/xe display runtime PM unified
   - Break i915 and xe panic dependency on struct intel_framebuffer
   - Streamline Pre/Post-CSC LUT loops
   - drop TGL DC3DO support
   - CDCLK santization
   - fix HDMI scrambling enable
   - fix phys bo pread/pwrite with offset
   - add missing nospec on parallel submit slot
   - fix some NULL derefs

  xe:
   - drop force_execlist module param
   - gate observation streams with perf_allow_cpu
   - skip FORCE_WC and vm_bound check for external dma-bufs
   - dmemcg eviction support
   - remove unused NVL-S GuC
   - TLB invalidation improvements
   - NVL-S updated PCI-IDs and w/a
   - madvise: optimise invalidation path
   - fix infinite gt-reset loop in timeout recovery
   - update TTM device benefical_order
   - wait on external BO kernel fences in exec ioctl
   - add/use more KLV helpers
   - sriov: disable display in admin only PF mode
   - add RAS GPU health indicator
   - optimise TTM populate for DONTNEED BO
   - drop force_probe for NVL-s
   - add debugfs for pcode info

  amdxdna:
   - disable device buffer export

  nova:
   - build nova-core/nova-drm from drivers/gpu
   - export nova-core rust symbols (workaround)
   - GSP boot process consolidation
   - Boot GSP with vGPU enabled
   - TLV firmware image format support
   - Hopper/Blackwell fixes and cleanups
   - I/O projection adoption

  tyr:
   - firmware loading and MCU boot
   - add generic slot manager + MMU
   - GPU VM support ARM64 LPAE page tables
   - add kernel buffer object for internal allocations
   - add parser for Mali CSF
   - add MCU booting

  nouveau:
   - race fixes
   - check instmem iomapping at first use
   - add dmemcg support
   - expose NVDEC channels
   - add scanline position/head state support for GSP

  qxl:
   - convert simple encoder to regular

  ethosu:
   - add perf counter support

  etnaviv:
   - force flush on power register ops

  msm:
   - support DSC configuration with slice_per_pkt > 1

  mxsfb:
   - fix disable sequence

  panthor:
   - support sparse mappings

  rockchip:
   - switch away from simple helpers
   - support YUV background color
   - fix layer config timeout
   - add edp support for rk3576
   - add batch command submission function

  rocket:
   - error handling and NULL ptr deref fixes

  sun4i:
   - switch away from simple helpers

  imagination:
   - mark BXM-4-64 MC1 as support

  host1x:
   - support tegra264

  tegra:
   - add DSI for tegra 20/30

  v3d:
   - reduce PM runtime autosuspend delay
   - scheduler fixes and refactoring
   - deprecate v3d 3.3 and 4.1
   - validate CPU job query boundaries

  hibmc:
   - improve plane format handling
   - switch to gem shmem

  mediatek:
   - cec: correct compat for mt7623-8167?

  exynos:
   - remove simple dependency
   - add error handling to encoder paths
   - take i2c adapter module reference"

* tag 'drm-next-2026-08-20' of https://gitlab.freedesktop.org/drm/kernel: (2074 commits)
  drm/xe/mcr: Take vcs1/vecs1 into account for first media slice
  drm/xe: Fix a bug in pc_adjust_freq_bounds()
  drm/xe: Fix xe_device_probe() failure
  drm/xe/drm_ras: Move has_drm_ras check to drm_ras layer
  drm/xe/ras: Fix boot-time ras error processing
  drm/amd/display: make DC_RUN_WITH_PREEMPTION_ENABLED misuse a build error
  drm/amd/pm: silence uninitialized variable warnings
  drm/amdgpu: skip BOs being torn down during GTT recovery
  drm/amdgpu: Reject UVD message with invalid number of h265 refs
  drm/amdgpu: keep PRT mappings off the vm_bo state lists
  drm/amdgpu: fix nbif 6.3.1 l1 low power not functional
  drm/amd/display: fix BT.2020 YCbCr output CSC matrices for DCE
  drm/amd/display: fix BT.2020 YCbCr limited output CSC matrix
  drm/amdgpu: Implement insert_end for VCE 3
  drm/amdgpu: Fix UVD min buffer sizes
  drm/amdgpu: Fix UVD decode image min size calculation
  drm/amdgpu: Fix UVD dpb min size calculation for H264
  drm/amdgpu: Reject UVD message with dimensions above 4096
  drm/amdgpu: check ASPM on the dGPU host link
  drm/radeon: fix autosuspend cleanup during teardown
  ...

8 files changed, 400 insertions, 115 deletions

diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 9f3090db2f16..b32c72a662b6 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -58,6 +58,7 @@ extern "C" {
 #define DRM_AMDGPU_USERQ_SIGNAL		0x17
 #define DRM_AMDGPU_USERQ_WAIT		0x18
 #define DRM_AMDGPU_GEM_LIST_HANDLES	0x19
+#define DRM_AMDGPU_PROC_OPTIONS		0x1A
 
 #define DRM_IOCTL_AMDGPU_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
 #define DRM_IOCTL_AMDGPU_GEM_MMAP	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@@ -79,6 +80,7 @@ extern "C" {
 #define DRM_IOCTL_AMDGPU_USERQ_SIGNAL	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal)
 #define DRM_IOCTL_AMDGPU_USERQ_WAIT	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait)
 #define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_LIST_HANDLES, struct drm_amdgpu_gem_list_handles)
+#define DRM_IOCTL_AMDGPU_PROC_OPTIONS	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_PROC_OPTIONS, struct drm_amdgpu_proc_options)
 
 /**
  * DOC: memory domains
@@ -1673,6 +1675,25 @@ struct drm_amdgpu_info_uq_metadata {
 #define AMDGPU_FAMILY_GC_11_5_4			154 /* GC 11.5.4 */
 #define AMDGPU_FAMILY_GC_12_0_0			152 /* GC 12.0.0 */
 
+/*
+ * Definition of user options
+ *
+ * option: AMDGPU_PROC_OPTIONS_OP_KFD_SIGBUS_DELAY
+ *    0:          Disable sigbus delay - SIGBUS will be raised immediately
+ *    0xFFFFFFFF: SIGBUS will not be raised
+ *    other:      Set the sigbus delay in milliseconds
+ */
+#define AMDGPU_PROC_OPTIONS_OP_KFD_SIGBUS_DELAY		0
+
+#define AMDGPU_PROC_OPTIONS_KFD_SIGBUS_DELAY_DISABLED	0xFFFFFFFFu
+
+struct drm_amdgpu_proc_options {
+	__u32 op;
+	struct {
+		__u32 value;
+	} kfd_sigbus_delay;
+};
+
 #if defined(__cplusplus)
 }
 #endif
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 3a4d4dc635bf..a103fdc0b3a3 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -1646,30 +1646,46 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
  * For multi-plane formats the above surfaces get merged into one plane for
  * each format plane, based on the required alignment only.
  *
- * Bits  Parameter                Notes
- * ----- ------------------------ ---------------------------------------------
+ * Bits    Parameter                Notes
+ * ------- ------------------------ ---------------------------------------------
+ *
+ * DRM format modifier fields on AMD GPUs:
+ *     7:0 TILE_VERSION             Values are AMD_FMT_MOD_TILE_VER_*
+ *    12:8 TILE                     Values are AMD_FMT_MOD_TILE_<version>_*
+ *      13 DCC                      Delta Color Compression, supported on GFX8 and newer
+ *   55:14 (chip specific)          See below for details, depends on GFX block version
+ *   63:56 Vendor                   Value is DRM_FORMAT_MOD_VENDOR_AMD
+ *
+ * Chip specific fields on Gfx9 and newer:
+ *      14 DCC_RETILE
+ *      15 DCC_PIPE_ALIGN
+ *      16 DCC_INDEPENDENT_64B
+ *      17 DCC_INDEPENDENT_128B
+ *   19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_*
+ *      20 DCC_CONSTANT_ENCODE
+ *   23:21 PIPE_XOR_BITS            Only for some chips
+ *   26:24 BANK_XOR_BITS            Only for some chips
+ *   29:27 PACKERS                  Only for some chips
+ *   32:30 RB                       Only for some chips
+ *   35:33 PIPE                     Only for some chips
+ *   55:36 -                        Reserved for future use, must be zero
+ *
+ * Chip specific fields on Gfx6-8:
+ *   16:14 MICROTILE                Micro tile format
+ *   21:17 PIPE_CONFIG              Number of pipes and how pipes are interleaved
+ *   24:22 TILE_SPLIT               Tile split size
+ *   26:25 BANK_WIDTH               Number of tiles in the X direction in the same bank
+ *   28:27 BANK_HEIGHT              Number of tiles in the Y direction in the same bank
+ *   30:29 MACRO_TILE_ASPECT        Macro tile aspect ratio
+ *   32:31 NUM_BANKS                Number of banks
+ *   55:33 -                        Reserved for future use, must be zero
  *
- *   7:0 TILE_VERSION             Values are AMD_FMT_MOD_TILE_VER_*
- *  12:8 TILE                     Values are AMD_FMT_MOD_TILE_<version>_*
- *    13 DCC
- *    14 DCC_RETILE
- *    15 DCC_PIPE_ALIGN
- *    16 DCC_INDEPENDENT_64B
- *    17 DCC_INDEPENDENT_128B
- * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_*
- *    20 DCC_CONSTANT_ENCODE
- * 23:21 PIPE_XOR_BITS            Only for some chips
- * 26:24 BANK_XOR_BITS            Only for some chips
- * 29:27 PACKERS                  Only for some chips
- * 32:30 RB                       Only for some chips
- * 35:33 PIPE                     Only for some chips
- * 55:36 -                        Reserved for future use, must be zero
  */
 #define AMD_FMT_MOD fourcc_mod_code(AMD, 0)
 
 #define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD)
 
-/* Reserve 0 for GFX8 and older */
+#define AMD_FMT_MOD_TILE_VER_GFX6 0
 #define AMD_FMT_MOD_TILE_VER_GFX9 1
 #define AMD_FMT_MOD_TILE_VER_GFX10 2
 #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
@@ -1677,6 +1693,23 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
 #define AMD_FMT_MOD_TILE_VER_GFX12 5
 
 /*
+ * Gfx6-8 tiling modes.
+ * A complete reference implementation is found in addrlib in the Mesa code base.
+ *
+ * - Microtiled modes (1D):
+ *   Pixel data is organized into micro tiles of 8x8 pixels.
+ *
+ * - Macrotiled modes (2D):
+ *   Micro tiles are further organized into macro tiles.
+ *   These are optimized for even load distribution among memory channels.
+ *
+ * Note that only THIN1 modes are exposed here.
+ * THICK and XTHICK are for 3D images and not relevant to DRM format modifiers.
+ */
+#define AMD_FMT_MOD_TILE_GFX6_1D_TILED_THIN1 0x2
+#define AMD_FMT_MOD_TILE_GFX6_2D_TILED_THIN1 0x4
+
+/*
  * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical
  * version.
  */
@@ -1774,6 +1807,146 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
 #define AMD_FMT_MOD_PIPE_SHIFT 33
 #define AMD_FMT_MOD_PIPE_MASK 0x7
 
+/*
+ * MICRO_TILE_MODE, 3 bits. Determines the micro tile format.
+ * Only relevant to Gfx6-8.
+ *
+ * DISPLAY - Displayable tiling
+ * THIN - Non-displayable tiling, a.k.a thin micro tiling
+ * DEPTH, THICK - not exposed, not relevant to DRM format modifier use cases
+ * ROTATED - not exposed, not implemented in Linux or Mesa
+ */
+#define AMD_FMT_MOD_MICROTILE_SHIFT 14ULL
+#define AMD_FMT_MOD_MICROTILE_MASK 0x7
+
+#define AMD_FMT_MOD_MICROTILE_DISPLAY 0x0
+#define AMD_FMT_MOD_MICROTILE_THIN 0x1
+
+/*
+ * PIPE_CONFIG, 5 bits. Number of pipes and how pipes are interleaved on the surface,
+ * which means the shader engine tile size and packer tile size.
+ * Typically matches the number of memory channels, or number of RBs.
+ * Only relevant to Gfx6-8 macro tiled modes.
+ *
+ * P<n>_<a>x<b>_<c>x<d>
+ * where:
+ * <n> - number of pipes
+ * <a>x<b> - shader engine tile size
+ * <c>x<d> - packer tile size
+ */
+#define AMD_FMT_MOD_PIPE_CONFIG_SHIFT 17ULL
+#define AMD_FMT_MOD_PIPE_CONFIG_MASK 0x1f
+
+#define AMD_FMT_MOD_PIPE_CONFIG_P2 0x0
+#define AMD_FMT_MOD_PIPE_CONFIG_P4_8x16 0x4
+#define AMD_FMT_MOD_PIPE_CONFIG_P4_16x16 0x5
+#define AMD_FMT_MOD_PIPE_CONFIG_P4_16x32 0x6
+#define AMD_FMT_MOD_PIPE_CONFIG_P4_32x32 0x7
+#define AMD_FMT_MOD_PIPE_CONFIG_P8_16x16_8x16 0x8
+#define AMD_FMT_MOD_PIPE_CONFIG_P8_16x32_8x16 0x9
+#define AMD_FMT_MOD_PIPE_CONFIG_P8_32x32_8x16 0xa
+#define AMD_FMT_MOD_PIPE_CONFIG_P8_16x32_16x16 0xb
+#define AMD_FMT_MOD_PIPE_CONFIG_P8_32x32_16x16 0xc
+#define AMD_FMT_MOD_PIPE_CONFIG_P8_32x32_16x32 0xd
+#define AMD_FMT_MOD_PIPE_CONFIG_P8_32x64_32x32 0xe
+#define AMD_FMT_MOD_PIPE_CONFIG_P16_32x32_8x16 0x10
+#define AMD_FMT_MOD_PIPE_CONFIG_P16_32x32_16x16 0x11
+
+/*
+ * TILE_SPLIT, 3 bits.
+ * Only relevant to Gfx6-8 macro tiled modes.
+ *
+ * On GFX6 (or with depth tiling modes on GFX7 and newer),
+ * the GFX block uses the GB_TILE_MODE.TILE_SPLIT field directly.
+ *
+ * On GFX7 and newer with non-depth tiling modes, the GFX block uses a
+ * split factor which is stored in the GB_TILE_MODE.SAMPLE_SPLIT field.
+ * SAMPLE_SPLIT may be: 0 - 1 byte; 1 - 2 bytes; 2 - 4 bytes; 3 - 8 bytes.
+ * The actual tile size and tile split bytes are calculated as follows:
+ *
+ *    bpp = ... <- bits per pixel in the current image
+ *    thickness = ... <- depends on array mode; may be: 1, 4, 8
+ *    num_samples = ... <- number of samples in the current image
+ *    tile_size_pixels = 8 * 8
+ *    tile_bytes_1x = thickness * tile_size_pixels * bpp / 8
+ *    sample_split_factor = 1 << SAMPLE_SPLIT
+ *    tile_split_bytes = clamp(tile_bytes_1x * sample_split_factor, 256, dram_row_size_bytes)
+ *    tile_bytes = clamp(tile_bytes_1x * num_samples, 64, tile_split_bytes)
+ *
+ * In both cases, the display block (DCE) has no SAMPLE_SPLIT
+ * and just needs the tile split bytes in the GRPH_CONTROL.GRPH_TILE_SPLIT field.
+ * To maximize compatibility between GFX6-7, we don't include the SAMPLE_SPLIT
+ * in the format modifiers.
+ *
+ * The actual tile split in bytes is: 64 << field value
+ * Possible values of this field:
+ *
+ * 0 - Tile split is 64 bytes
+ * 1 - Tile split is 128 bytes
+ * 2 - Tile split is 256 bytes
+ * 3 - Tile split is 512 bytes
+ * 4 - Tile split is 1 KiB
+ * 5 - Tile split is 2 KiB
+ * 6 - Tile split is 4 KiB
+ */
+#define AMD_FMT_MOD_TILE_SPLIT_SHIFT 22ULL
+#define AMD_FMT_MOD_TILE_SPLIT_MASK 0x7
+
+/*
+ * BANK_WIDTH, 2 bits. Number of tiles in the X direction in the same bank.
+ * Only relevant to Gfx6-8 macro tiled modes.
+ * The actual bank width is: 1 << field value
+ * Possible values:
+ *
+ * 0 - bank width is 1
+ * 1 - bank width is 2
+ * 2 - bank width is 4
+ * 3 - bank width is 8
+ */
+#define AMD_FMT_MOD_BANK_WIDTH_SHIFT 25ULL
+#define AMD_FMT_MOD_BANK_WIDTH_MASK 0x3
+
+/*
+ * BANK_HEIGHT, 2 bits. Number of tiles in the Y direction in the same bank.
+ * Only relevant to Gfx6-8 macro tiled modes.
+ * The actual bank height is: 1 << field value
+ * Possible values:
+ *
+ * 0 - bank height is 1
+ * 1 - bank height is 2
+ * 2 - bank height is 4
+ * 3 - bank height is 8
+ */
+#define AMD_FMT_MOD_BANK_HEIGHT_SHIFT 27ULL
+#define AMD_FMT_MOD_BANK_HEIGHT_MASK 0x3
+
+/*
+ * MACRO_TILE_ASPECT, 2 bits. Macro tile aspect ratio.
+ * Only relevant to Gfx6-8 macro tiled modes.
+ * Possible values:
+ *
+ * 0 - aspect ratio is 1:1
+ * 1 - aspect ratio is 4:1
+ * 2 - aspect ratio is 16:1
+ * 3 - aspect ratio is 64:1
+ */
+#define AMD_FMT_MOD_MACRO_TILE_ASPECT_SHIFT 29ULL
+#define AMD_FMT_MOD_MACRO_TILE_ASPECT_MASK 0x3
+
+/*
+ * NUM_BANKS, 2 bits. Number of banks.
+ * Only relevant to Gfx6-8 macro tiled modes.
+ * The actual number of banks is: 2 << field value
+ * Possible values:
+ *
+ * 0 - number of banks is 2
+ * 1 - number of banks is 4
+ * 2 - number of banks is 8
+ * 3 - number of banks is 16
+ */
+#define AMD_FMT_MOD_NUM_BANKS_SHIFT 31ULL
+#define AMD_FMT_MOD_NUM_BANKS_MASK 0x3
+
 #define AMD_FMT_MOD_SET(field, value) \
 	((__u64)(value) << AMD_FMT_MOD_##field##_SHIFT)
 #define AMD_FMT_MOD_GET(field, value) \
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 381a3e857d4e..bd435effdcee 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -155,6 +155,7 @@ extern "C" {
 /* Panel type property */
 #define DRM_MODE_PANEL_TYPE_UNKNOWN	0
 #define DRM_MODE_PANEL_TYPE_OLED	1
+#define DRM_MODE_PANEL_TYPE_LCD		2
 
 /*
  * DRM_MODE_ROTATE_<degrees>
diff --git a/include/uapi/drm/ethosu_accel.h b/include/uapi/drm/ethosu_accel.h
index af78bb4686d7..5b97d59a7806 100644
--- a/include/uapi/drm/ethosu_accel.h
+++ b/include/uapi/drm/ethosu_accel.h
@@ -43,6 +43,11 @@ enum drm_ethosu_ioctl_id {
 
 	/** @DRM_ETHOSU_SUBMIT: Submit a job and BOs to run. */
 	DRM_ETHOSU_SUBMIT,
+
+	DRM_ETHOSU_PERFMON_CREATE,
+	DRM_ETHOSU_PERFMON_DESTROY,
+	DRM_ETHOSU_PERFMON_GET_VALUES,
+	DRM_ETHOSU_PERFMON_SET_GLOBAL,
 };
 
 /**
@@ -79,6 +84,7 @@ struct drm_ethosu_npu_info {
 	__u32 config;
 
 	__u32 sram_size;
+	__u32 pmu_counters;
 };
 
 /**
@@ -220,10 +226,54 @@ struct drm_ethosu_submit {
 	/** Input: Number of jobs passed in. */
 	__u32 job_count;
 
-	/** Reserved, must be zero. */
+	/** Input: Id returned by DRM_ETHOSU_PERFMON_CREATE */
+	__u32 perfmon_id;
+};
+
+#define DRM_ETHOSU_MAX_PERF_EVENT_COUNTERS	8
+#define DRM_ETHOSU_MAX_PERF_COUNTERS \
+	(DRM_ETHOSU_MAX_PERF_EVENT_COUNTERS + 1)
+
+struct drm_ethosu_perfmon_create {
+	__u32 id;
+	__u32 ncounters;
+	__u16 counters[DRM_ETHOSU_MAX_PERF_EVENT_COUNTERS];
+};
+
+struct drm_ethosu_perfmon_destroy {
+	__u32 id;
 	__u32 pad;
 };
 
+/*
+ * Returns the values of the performance counters tracked by this
+ * perfmon (as an array of (ncounters + 1) u64 values).
+ *
+ * No implicit synchronization is performed, so the user has to
+ * guarantee that any jobs using this perfmon have already been
+ * completed.
+ */
+struct drm_ethosu_perfmon_get_values {
+	__u32 id;
+	__u32 pad;
+	__u64 values_ptr;
+};
+
+#define DRM_ETHOSU_PERFMON_CLEAR_GLOBAL    0x0001
+
+/**
+ * struct drm_ethosu_perfmon_set_global - ioctl to define a global performance
+ * monitor
+ *
+ * The global performance monitor will be used for all jobs. If a global
+ * performance monitor is defined, jobs with a self-defined performance
+ * monitor won't be allowed.
+ */
+struct drm_ethosu_perfmon_set_global {
+	__u32 flags;
+	__u32 id;
+};
+
 /**
  * DRM_IOCTL_ETHOSU() - Build a ethosu IOCTL number
  * @__access: Access type. Must be R, W or RW.
@@ -252,6 +302,14 @@ enum {
 		DRM_IOCTL_ETHOSU(WR, CMDSTREAM_BO_CREATE, cmdstream_bo_create),
 	DRM_IOCTL_ETHOSU_SUBMIT =
 		DRM_IOCTL_ETHOSU(WR, SUBMIT, submit),
+	DRM_IOCTL_ETHOSU_PERFMON_CREATE =
+		DRM_IOCTL_ETHOSU(WR, PERFMON_CREATE, perfmon_create),
+	DRM_IOCTL_ETHOSU_PERFMON_DESTROY =
+		DRM_IOCTL_ETHOSU(WR, PERFMON_DESTROY, perfmon_destroy),
+	DRM_IOCTL_ETHOSU_PERFMON_GET_VALUES =
+		DRM_IOCTL_ETHOSU(WR, PERFMON_GET_VALUES, perfmon_get_values),
+	DRM_IOCTL_ETHOSU_PERFMON_SET_GLOBAL =
+		DRM_IOCTL_ETHOSU(WR, PERFMON_SET_GLOBAL, perfmon_set_global),
 };
 
 #if defined(__cplusplus)
diff --git a/include/uapi/drm/nouveau_drm.h b/include/uapi/drm/nouveau_drm.h
index 1fa82fa6af38..c4905b3e4e91 100644
--- a/include/uapi/drm/nouveau_drm.h
+++ b/include/uapi/drm/nouveau_drm.h
@@ -89,6 +89,7 @@ struct drm_nouveau_getparam {
 #define NOUVEAU_FIFO_ENGINE_PPP 0x04
 #define NOUVEAU_FIFO_ENGINE_BSP 0x08
 #define NOUVEAU_FIFO_ENGINE_CE  0x30
+#define NOUVEAU_FIFO_ENGINE_NVDEC 0x300
 
 struct drm_nouveau_channel_alloc {
 	__u32     fb_ctxdma_handle;
diff --git a/include/uapi/drm/panthor_drm.h b/include/uapi/drm/panthor_drm.h
index 0e455d91e77d..a2ff0f4ec691 100644
--- a/include/uapi/drm/panthor_drm.h
+++ b/include/uapi/drm/panthor_drm.h
@@ -253,6 +253,9 @@ enum drm_panthor_dev_query_type {
 	 * @DRM_PANTHOR_DEV_QUERY_GROUP_PRIORITIES_INFO: Query allowed group priorities information.
 	 */
 	DRM_PANTHOR_DEV_QUERY_GROUP_PRIORITIES_INFO,
+
+	/** @DRM_PANTHOR_DEV_QUERY_MMU_INFO: Query MMU information. */
+	DRM_PANTHOR_DEV_QUERY_MMU_INFO,
 };
 
 /**
@@ -488,6 +491,16 @@ struct drm_panthor_timestamp_info {
 };
 
 /**
+ * struct drm_panthor_mmu_info - MMU information
+ *
+ * Structure grouping all queryable information relating to the MMU.
+ */
+struct drm_panthor_mmu_info {
+	/** @page_size_bitmap: Allowed page sizes */
+	__u64 page_size_bitmap;
+};
+
+/**
  * struct drm_panthor_group_priorities_info - Group priorities information
  *
  * Structure grouping all queryable information relating to the allowed group priorities.
@@ -602,6 +615,18 @@ enum drm_panthor_vm_bind_op_flags {
 	DRM_PANTHOR_VM_BIND_OP_MAP_UNCACHED = 1 << 2,
 
 	/**
+	 * @DRM_PANTHOR_VM_BIND_OP_MAP_SPARSE: Sparsely map a virtual memory range
+	 *
+	 * Only valid with DRM_PANTHOR_VM_BIND_OP_TYPE_MAP.
+	 *
+	 * When this flag is set, the whole vm_bind range is mapped over a dummy object in a cyclic
+	 * fashion, and all GPU reads from addresses in the range return undefined values. This flag
+	 * being set means drm_panthor_vm_bind_op::bo_offset and drm_panthor_vm_bind_op::bo_handle
+	 * must both be set to 0. DRM_PANTHOR_VM_BIND_OP_MAP_NOEXEC must also be set.
+	 */
+	DRM_PANTHOR_VM_BIND_OP_MAP_SPARSE = 1 << 3,
+
+	/**
 	 * @DRM_PANTHOR_VM_BIND_OP_TYPE_MASK: Mask used to determine the type of operation.
 	 */
 	DRM_PANTHOR_VM_BIND_OP_TYPE_MASK = (int)(0xfu << 28),
@@ -664,7 +689,6 @@ struct drm_panthor_vm_bind_op {
 	 * This array shall not be empty for sync-only operations.
 	 */
 	struct drm_panthor_obj_array syncs;
-
 };
 
 /**
diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index 48e9f1fdb78d..509202a7b13e 100644
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -2537,21 +2537,21 @@ struct drm_xe_exec_queue_set_property {
  * Refer to Documentation/netlink/specs/drm_ras.yaml for complete interface specification.
  *
  * Node Registration
- * =================
+ * -----------------
  *
  * The driver registers DRM RAS nodes for each error severity level.
  * enum drm_xe_ras_error_severity defines the node-id, while DRM_XE_RAS_ERROR_SEVERITY_NAMES maps
  * node-id to node-name.
  *
  * Error Classification
- * ====================
+ * --------------------
  *
  * Each node contains a list of error counters. Each error is identified by a error-id and
  * an error-name. enum drm_xe_ras_error_component defines the error-id, while
  * DRM_XE_RAS_ERROR_COMPONENT_NAMES maps error-id to error-name.
  *
  * User Interface
- * ==============
+ * --------------
  *
  * To retrieve error values of a error counter, userspace applications should
  * follow the below steps:
@@ -2589,6 +2589,12 @@ enum drm_xe_ras_error_component {
 	DRM_XE_RAS_ERR_COMP_CORE_COMPUTE = 1,
 	/** @DRM_XE_RAS_ERR_COMP_SOC_INTERNAL: SoC Internal Error */
 	DRM_XE_RAS_ERR_COMP_SOC_INTERNAL,
+	/** @DRM_XE_RAS_ERR_COMP_DEVICE_MEMORY: Device Memory Error */
+	DRM_XE_RAS_ERR_COMP_DEVICE_MEMORY,
+	/** @DRM_XE_RAS_ERR_COMP_PCIE: PCIe Subsystem Error */
+	DRM_XE_RAS_ERR_COMP_PCIE,
+	/** @DRM_XE_RAS_ERR_COMP_FABRIC: Fabric Subsystem Error */
+	DRM_XE_RAS_ERR_COMP_FABRIC,
 	/** @DRM_XE_RAS_ERR_COMP_MAX: Max Error */
 	DRM_XE_RAS_ERR_COMP_MAX	/* non-ABI */
 };
@@ -2606,7 +2612,10 @@ enum drm_xe_ras_error_component {
  */
 #define DRM_XE_RAS_ERROR_COMPONENT_NAMES {				\
 	[DRM_XE_RAS_ERR_COMP_CORE_COMPUTE] = "core-compute",		\
-	[DRM_XE_RAS_ERR_COMP_SOC_INTERNAL] = "soc-internal"		\
+	[DRM_XE_RAS_ERR_COMP_SOC_INTERNAL] = "soc-internal",		\
+	[DRM_XE_RAS_ERR_COMP_DEVICE_MEMORY] = "device-memory",		\
+	[DRM_XE_RAS_ERR_COMP_PCIE] = "pcie",				\
+	[DRM_XE_RAS_ERR_COMP_FABRIC] = "fabric",			\
 }
 
 #if defined(__cplusplus)
diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
index 9584b5aab727..749d196e2114 100644
--- a/include/uapi/linux/kfd_ioctl.h
+++ b/include/uapi/linux/kfd_ioctl.h
@@ -690,7 +690,7 @@ enum kfd_criu_op {
 };
 
 /**
- * kfd_ioctl_criu_args - Arguments perform CRIU operation
+ * struct kfd_ioctl_criu_args - Arguments perform CRIU operation
  * @devices:		[in/out] User pointer to memory location for devices information.
  * 			This is an array of type kfd_criu_device_bucket.
  * @bos:		[in/out] User pointer to memory location for BOs information
@@ -698,11 +698,11 @@ enum kfd_criu_op {
  * @priv_data:		[in/out] User pointer to memory location for private data
  * @priv_data_size:	[in/out] Size of priv_data in bytes
  * @num_devices:	[in/out] Number of GPUs used by process. Size of @devices array.
- * @num_bos		[in/out] Number of BOs used by process. Size of @bos array.
+ * @num_bos:		[in/out] Number of BOs used by process. Size of @bos array.
  * @num_objects:	[in/out] Number of objects used by process. Objects are opaque to
  *				 user application.
  * @pid:		[in/out] PID of the process being checkpointed
- * @op			[in] Type of operation (kfd_criu_op)
+ * @op:			[in] Type of operation (kfd_criu_op)
  *
  * Return: 0 on success, -errno on failure
  */
@@ -764,7 +764,7 @@ enum kfd_mmio_remap {
 #define KFD_IOCTL_SVM_FLAG_EXT_COHERENT        0x00000080
 
 /**
- * kfd_ioctl_svm_op - SVM ioctl operations
+ * enum kfd_ioctl_svm_op - SVM ioctl operations
  *
  * @KFD_IOCTL_SVM_OP_SET_ATTR: Modify one or more attributes
  * @KFD_IOCTL_SVM_OP_GET_ATTR: Query one or more attributes
@@ -786,7 +786,7 @@ enum kfd_ioctl_svm_location {
 };
 
 /**
- * kfd_ioctl_svm_attr_type - SVM attribute types
+ * enum kfd_ioctl_svm_attr_type - SVM attribute types
  *
  * @KFD_IOCTL_SVM_ATTR_PREFERRED_LOC: gpuid of the preferred location, 0 for
  *                                    system memory
@@ -815,7 +815,7 @@ enum kfd_ioctl_svm_attr_type {
 };
 
 /**
- * kfd_ioctl_svm_attribute - Attributes as pairs of type and value
+ * struct kfd_ioctl_svm_attribute - Attributes as pairs of type and value
  *
  * The meaning of the @value depends on the attribute type.
  *
@@ -828,7 +828,7 @@ struct kfd_ioctl_svm_attribute {
 };
 
 /**
- * kfd_ioctl_svm_args - Arguments for SVM ioctl
+ * struct kfd_ioctl_svm_args - Arguments for SVM ioctl
  *
  * @op specifies the operation to perform (see enum
  * @kfd_ioctl_svm_op).  @start_addr and @size are common for all
@@ -875,7 +875,7 @@ struct kfd_ioctl_svm_args {
 };
 
 /**
- * kfd_ioctl_set_xnack_mode_args - Arguments for set_xnack_mode
+ * struct kfd_ioctl_set_xnack_mode_args - Arguments for set_xnack_mode
  *
  * @xnack_enabled:       [in/out] Whether to enable XNACK mode for this process
  *
@@ -1055,15 +1055,15 @@ struct kfd_runtime_info {
 #define KFD_RUNTIME_ENABLE_MODE_TTMP_SAVE_MASK	2
 
 /**
- * kfd_ioctl_runtime_enable_args - Arguments for runtime enable
+ * struct kfd_ioctl_runtime_enable_args - Arguments for runtime enable
  *
  * Coordinates debug exception signalling and debug device enablement with runtime.
  *
- * @r_debug - pointer to user struct for sharing information between ROCr and the debuggger
- * @mode_mask - mask to set mode
+ * @r_debug: pointer to user struct for sharing information between ROCr and the debuggger
+ * @mode_mask: mask to set mode
  *	KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK - enable runtime for debugging, otherwise disable
  *	KFD_RUNTIME_ENABLE_MODE_TTMP_SAVE_MASK - enable trap temporary setup (ignore on disable)
- * @capabilities_mask - mask to notify runtime on what KFD supports
+ * @capabilities_mask: mask to notify runtime on what KFD supports
  *
  * Return - 0 on SUCCESS.
  *	  - EBUSY if runtime enable call already pending.
@@ -1158,17 +1158,15 @@ enum kfd_dbg_trap_operations {
 };
 
 /**
- * kfd_ioctl_dbg_trap_enable_args
- *
- *     Arguments for KFD_IOC_DBG_TRAP_ENABLE.
+ * struct kfd_ioctl_dbg_trap_enable_args - Arguments for KFD_IOC_DBG_TRAP_ENABLE.
  *
  *     Enables debug session for target process. Call @op KFD_IOC_DBG_TRAP_DISABLE in
  *     kfd_ioctl_dbg_trap_args to disable debug session.
  *
- *     @exception_mask (IN)	- exceptions to raise to the debugger
- *     @rinfo_ptr      (IN)	- pointer to runtime info buffer (see kfd_runtime_info)
- *     @rinfo_size     (IN/OUT)	- size of runtime info buffer in bytes
- *     @dbg_fd	       (IN)	- fd the KFD will nofify the debugger with of raised
+ *     @exception_mask: (IN) - exceptions to raise to the debugger
+ *     @rinfo_ptr:      (IN) - pointer to runtime info buffer (see kfd_runtime_info)
+ *     @rinfo_size:     (IN/OUT) - size of runtime info buffer in bytes
+ *     @dbg_fd:	        (IN) - fd the KFD will nofify the debugger with of raised
  *				  exceptions set in exception_mask.
  *
  *     Generic errors apply (see kfd_dbg_trap_operations).
@@ -1188,15 +1186,14 @@ struct kfd_ioctl_dbg_trap_enable_args {
 };
 
 /**
- * kfd_ioctl_dbg_trap_send_runtime_event_args
- *
+ * struct kfd_ioctl_dbg_trap_send_runtime_event_args - Arguments for
+ * KFD_IOC_DBG_TRAP_SEND_RUNTIME_EVENT.
  *
- *     Arguments for KFD_IOC_DBG_TRAP_SEND_RUNTIME_EVENT.
  *     Raises exceptions to runtime.
  *
- *     @exception_mask (IN) - exceptions to raise to runtime
- *     @gpu_id	       (IN) - target device id
- *     @queue_id       (IN) - target queue id
+ *     @exception_mask: (IN) - exceptions to raise to runtime
+ *     @gpu_id:	        (IN) - target device id
+ *     @queue_id:       (IN) - target queue id
  *
  *     Generic errors apply (see kfd_dbg_trap_operations).
  *     Return - 0 on SUCCESS.
@@ -1213,12 +1210,12 @@ struct kfd_ioctl_dbg_trap_send_runtime_event_args {
 };
 
 /**
- * kfd_ioctl_dbg_trap_set_exceptions_enabled_args
+ * struct kfd_ioctl_dbg_trap_set_exceptions_enabled_args - Arguments for
+ * KFD_IOC_SET_EXCEPTIONS_ENABLED
  *
- *     Arguments for KFD_IOC_SET_EXCEPTIONS_ENABLED
  *     Set new exceptions to be raised to the debugger.
  *
- *     @exception_mask (IN) - new exceptions to raise the debugger
+ *     @exception_mask: (IN) - new exceptions to raise the debugger
  *
  *     Generic errors apply (see kfd_dbg_trap_operations).
  *     Return - 0 on SUCCESS.
@@ -1228,16 +1225,16 @@ struct kfd_ioctl_dbg_trap_set_exceptions_enabled_args {
 };
 
 /**
- * kfd_ioctl_dbg_trap_set_wave_launch_override_args
+ * struct kfd_ioctl_dbg_trap_set_wave_launch_override_args - Arguments for
+ * KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE
  *
- *     Arguments for KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE
  *     Enable HW exceptions to raise trap.
  *
- *     @override_mode	     (IN)     - see kfd_dbg_trap_override_mode
- *     @enable_mask	     (IN/OUT) - reference kfd_dbg_trap_mask.
+ *     @override_mode:	     (IN)     - see kfd_dbg_trap_override_mode
+ *     @enable_mask:	     (IN/OUT) - reference kfd_dbg_trap_mask.
  *					IN is the override modes requested to be enabled.
  *					OUT is referenced in Return below.
- *     @support_request_mask (IN/OUT) - reference kfd_dbg_trap_mask.
+ *     @support_request_mask: (IN/OUT) - reference kfd_dbg_trap_mask.
  *					IN is the override modes requested for support check.
  *					OUT is referenced in Return below.
  *
@@ -1254,36 +1251,38 @@ struct kfd_ioctl_dbg_trap_set_wave_launch_override_args {
 	__u32 override_mode;
 	__u32 enable_mask;
 	__u32 support_request_mask;
+	/* private: */
 	__u32 pad;
 };
 
 /**
- * kfd_ioctl_dbg_trap_set_wave_launch_mode_args
+ * struct kfd_ioctl_dbg_trap_set_wave_launch_mode_args - Arguments for
+ * KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE
  *
- *     Arguments for KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE
  *     Set wave launch mode.
  *
- *     @mode (IN) - see kfd_dbg_trap_wave_launch_mode
+ *     @launch_mode: (IN) - see kfd_dbg_trap_wave_launch_mode
  *
  *     Generic errors apply (see kfd_dbg_trap_operations).
  *     Return - 0 on SUCCESS.
  */
 struct kfd_ioctl_dbg_trap_set_wave_launch_mode_args {
 	__u32 launch_mode;
+	/* private: */
 	__u32 pad;
 };
 
 /**
- * kfd_ioctl_dbg_trap_suspend_queues_ags
+ * struct kfd_ioctl_dbg_trap_suspend_queues_args - Arguments for
+ * KFD_IOC_DBG_TRAP_SUSPEND_QUEUES
  *
- *     Arguments for KFD_IOC_DBG_TRAP_SUSPEND_QUEUES
  *     Suspend queues.
  *
- *     @exception_mask	(IN) - raised exceptions to clear
- *     @queue_array_ptr (IN) - pointer to array of queue ids (u32 per queue id)
+ *     @exception_mask:	(IN) - raised exceptions to clear
+ *     @queue_array_ptr: (IN) - pointer to array of queue ids (u32 per queue id)
  *			       to suspend
- *     @num_queues	(IN) - number of queues to suspend in @queue_array_ptr
- *     @grace_period	(IN) - wave time allowance before preemption
+ *     @num_queues:	(IN) - number of queues to suspend in @queue_array_ptr
+ *     @grace_period:	(IN) - wave time allowance before preemption
  *			       per 1K GPU clock cycle unit
  *
  *     Generic errors apply (see kfd_dbg_trap_operations).
@@ -1311,14 +1310,14 @@ struct kfd_ioctl_dbg_trap_suspend_queues_args {
 };
 
 /**
- * kfd_ioctl_dbg_trap_resume_queues_args
+ * struct kfd_ioctl_dbg_trap_resume_queues_args - Arguments for
+ * KFD_IOC_DBG_TRAP_RESUME_QUEUES
  *
- *     Arguments for KFD_IOC_DBG_TRAP_RESUME_QUEUES
  *     Resume queues.
  *
- *     @queue_array_ptr (IN) - pointer to array of queue ids (u32 per queue id)
+ *     @queue_array_ptr: (IN) - pointer to array of queue ids (u32 per queue id)
  *			       to resume
- *     @num_queues	(IN) - number of queues to resume in @queue_array_ptr
+ *     @num_queues:	(IN) - number of queues to resume in @queue_array_ptr
  *
  *     Generic errors apply (see kfd_dbg_trap_operations).
  *     Return - Number of queues resumed on SUCCESS.
@@ -1331,20 +1330,21 @@ struct kfd_ioctl_dbg_trap_suspend_queues_args {
 struct kfd_ioctl_dbg_trap_resume_queues_args {
 	__u64 queue_array_ptr;
 	__u32 num_queues;
+	/* private: */
 	__u32 pad;
 };
 
 /**
- * kfd_ioctl_dbg_trap_set_node_address_watch_args
+ * struct kfd_ioctl_dbg_trap_set_node_address_watch_args - Arguments for
+ * KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH
  *
- *     Arguments for KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH
  *     Sets address watch for device.
  *
- *     @address	(IN)  - watch address to set
- *     @mode    (IN)  - see kfd_dbg_trap_address_watch_mode
- *     @mask    (IN)  - watch address mask
- *     @gpu_id  (IN)  - target gpu to set watch point
- *     @id      (OUT) - watch id allocated
+ *     @address: (IN)  - watch address to set
+ *     @mode:    (IN)  - see kfd_dbg_trap_address_watch_mode
+ *     @mask:    (IN)  - watch address mask
+ *     @gpu_id:  (IN)  - target gpu to set watch point
+ *     @id:      (OUT) - watch id allocated
  *
  *     Generic errors apply (see kfd_dbg_trap_operations).
  *     Return - 0 on SUCCESS.
@@ -1361,13 +1361,13 @@ struct kfd_ioctl_dbg_trap_set_node_address_watch_args {
 };
 
 /**
- * kfd_ioctl_dbg_trap_clear_node_address_watch_args
+ * struct kfd_ioctl_dbg_trap_clear_node_address_watch_args - Arguments for
+ * KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH
  *
- *     Arguments for KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH
  *     Clear address watch for device.
  *
- *     @gpu_id  (IN)  - target device to clear watch point
- *     @id      (IN) - allocated watch id to clear
+ *     @gpu_id:  (IN)  - target device to clear watch point
+ *     @id:      (IN) - allocated watch id to clear
  *
  *     Generic errors apply (see kfd_dbg_trap_operations).
  *     Return - 0 on SUCCESS.
@@ -1380,12 +1380,12 @@ struct kfd_ioctl_dbg_trap_clear_node_address_watch_args {
 };
 
 /**
- * kfd_ioctl_dbg_trap_set_flags_args
+ * struct kfd_ioctl_dbg_trap_set_flags_args - Arguments for
+ * KFD_IOC_DBG_TRAP_SET_FLAGS
  *
- *     Arguments for KFD_IOC_DBG_TRAP_SET_FLAGS
  *     Sets flags for wave behaviour.
  *
- *     @flags (IN/OUT) - IN = flags to enable, OUT = flags previously enabled
+ *     @flags: (IN/OUT) - IN = flags to enable, OUT = flags previously enabled
  *
  *     Generic errors apply (see kfd_dbg_trap_operations).
  *     Return - 0 on SUCCESS.
@@ -1393,13 +1393,13 @@ struct kfd_ioctl_dbg_trap_clear_node_address_watch_args {
  */
 struct kfd_ioctl_dbg_trap_set_flags_args {
 	__u32 flags;
+	/* private: */
 	__u32 pad;
 };
 
 /**
- * kfd_ioctl_dbg_trap_query_debug_event_args
- *
- *     Arguments for KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT
+ * struct kfd_ioctl_dbg_trap_query_debug_event_args - Arguments for
+ * KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT
  *
  *     Find one or more raised exceptions. This function can return multiple
  *     exceptions from a single queue or a single device with one call. To find
@@ -1409,9 +1409,9 @@ struct kfd_ioctl_dbg_trap_set_flags_args {
  *     However, clearing an exception prevents retrieving further information
  *     about it with KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO.
  *
- *     @exception_mask (IN/OUT) - exception to clear (IN) and raised (OUT)
- *     @gpu_id	       (OUT)    - gpu id of exceptions raised
- *     @queue_id       (OUT)    - queue id of exceptions raised
+ *     @exception_mask: (IN/OUT) - exception to clear (IN) and raised (OUT)
+ *     @gpu_id:	        (OUT)    - gpu id of exceptions raised
+ *     @queue_id:       (OUT)    - queue id of exceptions raised
  *
  *     Generic errors apply (see kfd_dbg_trap_operations).
  *     Return - 0 on raised exception found
@@ -1426,16 +1426,16 @@ struct kfd_ioctl_dbg_trap_query_debug_event_args {
 };
 
 /**
- * kfd_ioctl_dbg_trap_query_exception_info_args
+ * struct kfd_ioctl_dbg_trap_query_exception_info_args - Arguments for
+ * KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO
  *
- *     Arguments KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO
  *     Get additional info on raised exception.
  *
- *     @info_ptr	(IN)	 - pointer to exception info buffer to copy to
- *     @info_size	(IN/OUT) - exception info buffer size (bytes)
- *     @source_id	(IN)     - target gpu or queue id
- *     @exception_code	(IN)     - target exception
- *     @clear_exception	(IN)     - clear raised @exception_code exception
+ *     @info_ptr:	(IN)	 - pointer to exception info buffer to copy to
+ *     @info_size:	(IN/OUT) - exception info buffer size (bytes)
+ *     @source_id:	(IN)     - target gpu or queue id
+ *     @exception_code:	(IN)     - target exception
+ *     @clear_exception: (IN)     - clear raised @exception_code exception
  *				   (0 = false, 1 = true)
  *
  *     Generic errors apply (see kfd_dbg_trap_operations).
@@ -1455,20 +1455,20 @@ struct kfd_ioctl_dbg_trap_query_exception_info_args {
 };
 
 /**
- * kfd_ioctl_dbg_trap_get_queue_snapshot_args
+ * struct kfd_ioctl_dbg_trap_queue_snapshot_args - Arguments for
+ * KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT
  *
- *     Arguments KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT
  *     Get queue information.
  *
- *     @exception_mask	 (IN)	  - exceptions raised to clear
- *     @snapshot_buf_ptr (IN)	  - queue snapshot entry buffer (see kfd_queue_snapshot_entry)
- *     @num_queues	 (IN/OUT) - number of queue snapshot entries
+ *     @exception_mask:	 (IN)	  - exceptions raised to clear
+ *     @snapshot_buf_ptr: (IN)	  - queue snapshot entry buffer (see kfd_queue_snapshot_entry)
+ *     @num_queues:	 (IN/OUT) - number of queue snapshot entries
  *         The debugger specifies the size of the array allocated in @num_queues.
  *         KFD returns the number of queues that actually existed. If this is
  *         larger than the size specified by the debugger, KFD will not overflow
  *         the array allocated by the debugger.
  *
- *     @entry_size	 (IN/OUT) - size per entry in bytes
+ *     @entry_size:	 (IN/OUT) - size per entry in bytes
  *         The debugger specifies sizeof(struct kfd_queue_snapshot_entry) in
  *         @entry_size. KFD returns the number of bytes actually populated per
  *         entry. The debugger should use the KFD_IOCTL_MINOR_VERSION to determine,
@@ -1491,20 +1491,20 @@ struct kfd_ioctl_dbg_trap_queue_snapshot_args {
 };
 
 /**
- * kfd_ioctl_dbg_trap_get_device_snapshot_args
+ * struct kfd_ioctl_dbg_trap_device_snapshot_args - Arguments for
+ * KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT
  *
- *     Arguments for KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT
  *     Get device information.
  *
- *     @exception_mask	 (IN)	  - exceptions raised to clear
- *     @snapshot_buf_ptr (IN)	  - pointer to snapshot buffer (see kfd_dbg_device_info_entry)
- *     @num_devices	 (IN/OUT) - number of debug devices to snapshot
+ *     @exception_mask:	  (IN)	  - exceptions raised to clear
+ *     @snapshot_buf_ptr: (IN)	  - pointer to snapshot buffer (see kfd_dbg_device_info_entry)
+ *     @num_devices:	  (IN/OUT) - number of debug devices to snapshot
  *         The debugger specifies the size of the array allocated in @num_devices.
  *         KFD returns the number of devices that actually existed. If this is
  *         larger than the size specified by the debugger, KFD will not overflow
  *         the array allocated by the debugger.
  *
- *     @entry_size	 (IN/OUT) - size per entry in bytes
+ *     @entry_size:	  (IN/OUT) - size per entry in bytes
  *         The debugger specifies sizeof(struct kfd_dbg_device_info_entry) in
  *         @entry_size. KFD returns the number of bytes actually populated. The
  *         debugger should use KFD_IOCTL_MINOR_VERSION to determine, which fields
@@ -1527,12 +1527,10 @@ struct kfd_ioctl_dbg_trap_device_snapshot_args {
 };
 
 /**
- * kfd_ioctl_dbg_trap_args
- *
- * Arguments to debug target process.
+ * struct kfd_ioctl_dbg_trap_args - Arguments to debug target process.
  *
- *     @pid - target process to debug
- *     @op  - debug operation (see kfd_dbg_trap_operations)
+ *     @pid: target process to debug
+ *     @op:  debug operation (see kfd_dbg_trap_operations)
  *
  *     @op determines which union struct args to use.
  *     Refer to kern docs for each kfd_ioctl_dbg_trap_*_args struct.
@@ -1567,7 +1565,7 @@ enum kfd_profiler_ops {
 };
 
 /**
- * Enables/Disables GPU Specific profiler settings
+ * struct kfd_ioctl_pmc_settings - Enables/Disables GPU Specific profiler settings
  */
 struct kfd_ioctl_pmc_settings {
 	__u32 gpu_id;             /* This is the user_gpu_id */