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authorIvan Vecera <ivecera@redhat.com>2026-06-30 14:55:33 +0200
committerPaolo Abeni <pabeni@redhat.com>2026-07-06 14:45:05 +0200
commit0cc8348a9786727e3622f833f442e8b45e2d363b (patch)
tree94a6af0720050e8392cb91014b71e84c7ba01e4a /include/uapi/linux
parentb1d0c412088e3908821ef2ec52e2c0e5e7f5a535 (diff)
dpll: add DPLL_PIN_TYPE_INT_NCO pin type
Add DPLL_PIN_TYPE_INT_NCO pin type for virtual pins representing the NCO mode of a DPLL. When connected as a DPLL input, the DPLL enters NCO mode where the output frequency is adjusted by the host via the PTP clock interface. Update the fractional-frequency-offset and fractional-frequency- offset-ppt attribute documentation to note that for INT_NCO pins these attributes represent the DPLL's current output frequency offset from its nominal frequency. Reviewed-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ivan Vecera <ivecera@redhat.com> Link: https://patch.msgid.link/20260630125536.720717-3-ivecera@redhat.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Diffstat (limited to 'include/uapi/linux')
-rw-r--r--include/uapi/linux/dpll.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/include/uapi/linux/dpll.h b/include/uapi/linux/dpll.h
index 5d7ca6a413cd..85b898b1db5e 100644
--- a/include/uapi/linux/dpll.h
+++ b/include/uapi/linux/dpll.h
@@ -129,6 +129,9 @@ enum dpll_type {
* @DPLL_PIN_TYPE_SYNCE_ETH_PORT: ethernet port PHY's recovered clock
* @DPLL_PIN_TYPE_INT_OSCILLATOR: device internal oscillator
* @DPLL_PIN_TYPE_GNSS: GNSS recovered clock
+ * @DPLL_PIN_TYPE_INT_NCO: Device internal numerically controlled oscillator.
+ * When connected as a DPLL input, the DPLL enters NCO mode where the output
+ * frequency is adjusted by the host via the PTP clock interface.
*/
enum dpll_pin_type {
DPLL_PIN_TYPE_MUX = 1,
@@ -136,6 +139,7 @@ enum dpll_pin_type {
DPLL_PIN_TYPE_SYNCE_ETH_PORT,
DPLL_PIN_TYPE_INT_OSCILLATOR,
DPLL_PIN_TYPE_GNSS,
+ DPLL_PIN_TYPE_INT_NCO,
/* private: */
__DPLL_PIN_TYPE_MAX,