Merge tag 'clk-misc-round-two-for-v7.3' of ssh://github.com/masneyb/linux into clk-pile

Pull clk patches from Brian Masney:

 - New clock controller drivers for the Cix Sky1 audio subsystem (AUDSS),
   UltraRISC DP1000, and MediaTek MT8173 MFG_TOP, along with their devicetree
   bindings. Si549 support was added to the existing si544 driver.
 - New clock and reset support for the Aspeed AST2700 PECI controller and Airoha
   EN7523 PCIe PERSTOUT reset lines.
 - The clk core gains devm_clk_bulk_get_enable() as the mandatory counterpart to
   the existing optional variant, and exports
   devm_clk_hw_register_composite_pdata() for modular drivers.
 - Tegra gets a proper EMC clock implementation for Tegra114, 48MHz pll_p_out1
   support needed for UEFI on Surface2, and the Xilinx clocking-wizard gains PLL
   charge pump/lock parameter programming during dynamic reconfiguration.
 - Bug fixes for a NULL pointer dereference from uninitialized clk_init_data in
   the eswin driver, an IO remap leak in the MediaTek pllfh error path, inverted
   gate control for MT8135 devapc_ck, a missing OF node put in tegra124-emc on
   registration failure, a prepare reference leak in the palmas driver,
   unregistered PLLs on MT6735 probe failure, a missing kasprintf NULL check in
   pmc_atom, PCIe warm boot instability in the Airoha EN7523 driver, and a
   clocking-wizard clock difference detection bug.
 - Various cleanups across tegra, st, and mvebu providers to stop misusing the
   consumer clock API, along with other minor fixes and improvements.

Signed-off-by: Brian Masney <bmasney@redhat.com>

* tag 'clk-misc-round-two-for-v7.3' of ssh://github.com/masneyb/linux: (45 commits)
  clk: tegra: set up proper EMC clock implementation for Tegra114
  clk: clocking-wizard: remove 20kHz restriction
  clk: clocking-wizard: optimize clock search
  clk: clocking-wizard: fix clock difference detection
  clk: mediatek: mt8135: Fix inverted gate control for devapc_ck
  clk: clocking-wizard: Program PLL CP/RES and lock parameters on reconfig
  clk: tegra: support 48MHz clock for pll_p_out1
  clk: aspeed: add AST2700 PECI clock
  dt-bindings: clock: ast2700: add PECI clock
  clk: mediatek: Add mt8173-mfgtop driver
  dt-bindings: clock: mediatek: Add mt8173 mfgtop
  clk: tegra: clean-up simple provider misuse of the consumer API
  clk: st: clean-up simple provider misuse of the consumer API
  clk: mvebu: clean-up simple provider misuse of the consumer API
  clk: remove conditional return with no effect
  clk: Add devm_clk_bulk_get_enable()
  clk: en7523: add support for dedicated PCIe PERSTOUT reset
  dt-bindings: clock: airoha: Add additional reset for PCIe PERSTOUT
  arm64: dts: cix: sky1: add audss cru
  reset: cix: add sky1 audss auxiliary reset driver
  ...

1 files changed, 25 insertions, 2 deletions

diff --git a/include/linux/clk.h b/include/linux/clk.h
index 998ba3f261da..db9cf184fd99 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -503,6 +503,22 @@ int __must_check devm_clk_bulk_get(struct device *dev, int num_clks,
 int __must_check devm_clk_bulk_get_optional(struct device *dev, int num_clks,
 					    struct clk_bulk_data *clks);
 /**
+ * devm_clk_bulk_get_enable - Get and enable bulk clocks (managed)
+ * @dev: device for clock "consumer"
+ * @num_clks: the number of clk_bulk_data
+ * @clks: pointer to the clk_bulk_data table of consumer
+ *
+ * Behaves the same as devm_clk_bulk_get() but also prepares and enables the
+ * clocks in one operation with management. The clks will automatically be
+ * disabled, unprepared and freed when the device is unbound.
+ *
+ * Return: 0 if all clocks specified in clk_bulk_data table are obtained and
+ * enabled successfully. Otherwise returns valid IS_ERR() condition containing
+ * errno.
+ */
+int __must_check devm_clk_bulk_get_enable(struct device *dev, int num_clks,
+					  struct clk_bulk_data *clks);
+/**
  * devm_clk_bulk_get_optional_enable - Get and enable optional bulk clocks (managed)
  * @dev: device for clock "consumer"
  * @num_clks: the number of clk_bulk_data
@@ -951,8 +967,8 @@ int clk_set_parent(struct clk *clk, struct clk *parent);
  * clk_get_parent - get the parent clock source for this clock
  * @clk: clock source
  *
- * Returns struct clk corresponding to parent clock source, or
- * valid IS_ERR() condition containing errno.
+ * Returns struct clk corresponding to parent clock source, or NULL
+ * if clk is NULL.
  */
 struct clk *clk_get_parent(struct clk *clk);
 
@@ -1052,6 +1068,13 @@ static inline int __must_check devm_clk_bulk_get_optional(struct device *dev,
 	return 0;
 }
 
+static inline int __must_check devm_clk_bulk_get_enable(struct device *dev,
+							int num_clks,
+							struct clk_bulk_data *clks)
+{
+	return 0;
+}
+
 static inline int __must_check devm_clk_bulk_get_optional_enable(struct device *dev,
 								 int num_clks,
 								 struct clk_bulk_data *clks)