Merge tag 'renesas-clk-for-v7.3-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add RTC and display clocks on RZ/T2H and RZ/N2H
 - Add audio and display clocks and resets on RZ/G3E
 - Add SDHI, GPU, and USB2.0 clocks and resets on RZ/G3L
 - Update the maintainer for the VersaClock 7 driver
 - Add CAN-FD clocks and resets for RZ/G3S

* tag 'renesas-clk-for-v7.3-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: r9a08g045: Add clocks and resets for CAN-FD
  dt-bindings: clock: renesas,versaclock7: Update maintainer
  clk: renesas: r9a09g047: Add LVDS clocks and resets
  clk: renesas: r9a09g077: Add LCDC and PLL3 clock support for RZ/T2H display pipeline
  clk: renesas: rzv2h-cpg: Extract PLL calculation helpers into shared library
  clk: renesas: rzv2h-cpg: Use per-SoC PLL reference frequency for calculations
  clk: renesas: r9a08g046: Add USB2.0 clock and reset entries
  clk: renesas: r9a09g077: Add RTC clocks
  clk: renesas: cpg-mssr: Implement dedicated MSTP delay logic for RZ/T2H LCDC and RTC
  clk: renesas: r9a08g046: Add clock and reset entries for GE3D
  clk: renesas: r9a08g046: Add clock and reset entries for SDHI
  clk: renesas: r9a09g047: Add audio clock and reset support
  dt-bindings: clock: renesas: Add audio clock inputs for RZ/V2H family
  dt-bindings: clock: renesas,r9a09g077/87: Add PCLKRTC clock ID
  dt-bindings: clock: renesas,r9a09g077/87: Add LCDC_CLKD clock ID

1 files changed, 21 insertions, 13 deletions

diff --git a/include/linux/clk/renesas.h b/include/linux/clk/renesas.h
index 0949400f44de..c9495558cd5c 100644
--- a/include/linux/clk/renesas.h
+++ b/include/linux/clk/renesas.h
@@ -53,6 +53,9 @@ static inline void rzg2l_cpg_dsi_div_set_divider(u8 divider, int target) { }
  * various parameters used to configure a PLL. These limits ensure
  * the PLL operates within valid and stable ranges.
  *
+ * @input_fref: Reference input frequency to the PLL (in Hz). If set
+ * to 0, a default value of 24MHz is used.
+ *
  * @fout: Output frequency range (in MHz)
  * @fout.min: Minimum allowed output frequency
  * @fout.max: Maximum allowed output frequency
@@ -78,6 +81,8 @@ static inline void rzg2l_cpg_dsi_div_set_divider(u8 divider, int target) { }
  * @k.max: Maximum delta-sigma value
  */
 struct rzv2h_pll_limits {
+	u32 input_fref;
+
 	struct {
 		u32 min;
 		u32 max;
@@ -184,28 +189,31 @@ struct rzv2h_pll_div_pars {
 		.k = { .min = -32768, .max = 32767 },			\
 	}								\
 
-#ifdef CONFIG_CLK_RZV2H
-bool rzv2h_get_pll_pars(const struct rzv2h_pll_limits *limits,
-			struct rzv2h_pll_pars *pars, u64 freq_millihz);
+#ifdef CONFIG_CLK_RZV2H_CPG_LIB
+bool rzv2h_cpg_get_pll_pars(const struct rzv2h_pll_limits *limits,
+			    struct rzv2h_pll_pars *pars, u64 freq_millihz);
 
-bool rzv2h_get_pll_divs_pars(const struct rzv2h_pll_limits *limits,
-			     struct rzv2h_pll_div_pars *pars,
-			     const u8 *table, u8 table_size, u64 freq_millihz);
+bool rzv2h_cpg_get_pll_divs_pars(const struct rzv2h_pll_limits *limits,
+				 struct rzv2h_pll_div_pars *pars,
+				 const u8 *table, u8 table_size, u64 freq_millihz);
 #else
-static inline bool rzv2h_get_pll_pars(const struct rzv2h_pll_limits *limits,
-				      struct rzv2h_pll_pars *pars,
-				      u64 freq_millihz)
+static inline bool rzv2h_cpg_get_pll_pars(const struct rzv2h_pll_limits *limits,
+					  struct rzv2h_pll_pars *pars,
+					  u64 freq_millihz)
 {
 	return false;
 }
 
-static inline bool rzv2h_get_pll_divs_pars(const struct rzv2h_pll_limits *limits,
-					   struct rzv2h_pll_div_pars *pars,
-					   const u8 *table, u8 table_size,
-					   u64 freq_millihz)
+static inline bool rzv2h_cpg_get_pll_divs_pars(const struct rzv2h_pll_limits *limits,
+					       struct rzv2h_pll_div_pars *pars,
+					       const u8 *table, u8 table_size,
+					       u64 freq_millihz)
 {
 	return false;
 }
 #endif
 
+#define rzv2h_get_pll_pars	rzv2h_cpg_get_pll_pars
+#define rzv2h_get_pll_divs_pars	rzv2h_cpg_get_pll_divs_pars
+
 #endif