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authorGustavo Sousa <gustavo.sousa@intel.com>2026-05-14 18:44:46 -0300
committerGustavo Sousa <gustavo.sousa@intel.com>2026-05-15 18:05:12 -0300
commit75f65f1a4c06da1d87f28570a9d4cdad28f13360 (patch)
treed4d20942bde5759f6431dd6247465512223bda11 /include/linux
parenta672725fdbfc3ea430130039d677c7dc98d59df8 (diff)
drm/xe: Define and use MCR version of COMMON_SLICE_CHICKEN4
The register COMMON_SLICE_CHICKEN4 is a MCR register on both Xe2 and Xe3. Let's make sure to define a MCR version of it and use it for the relevant IP versions. Use XEHP_ as prefix for the register name, since it is MCR as of Xe_HP. v2: - Also change for one entry in lrc_tunnings, which was caught by manual testing and add corresponging Fixes tag in commit message. (Gustavo) Fixes: 8d6f16f1f082 ("drm/xe: Extend Wa_22021007897 to Xe3 platforms") Fixes: e5c13e2c505b ("drm/xe/xe2hpg: Add Wa_22021007897") Fixes: 8ccf5f6b2295 ("drm/xe/tuning: Apply windower hardware filtering setting on Xe3 and Xe3p") Bspec: 66534, 71185, 74417 Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patch.msgid.link/20260514-rtp-mcr-check-v3-3-30dd47855fee@intel.com Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Diffstat (limited to 'include/linux')
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