diff options
| author | Devendra K Verma <devendra.verma@amd.com> | 2026-07-13 12:18:54 +0530 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2026-07-17 17:32:22 +0530 |
| commit | 64173b6b7609acb88fb763041c9e496caa6e834d (patch) | |
| tree | 586c62ba1fe429ec41338ed93129d92b57901fc8 /include/linux | |
| parent | 643c1e1ae3eb3cd9be31e83c2240e41849a6cb56 (diff) | |
dmaengine: dw-edma: Enable HDMA 64R/W Channels
As per 'Designware Cores PCI Express Controller Databook',
Section 7.1 - Overview, HDMA supports 64 Read and 64 Write
channels. Current controller driver supports up to 8 read and
write channels only. In order to utilize all the channels the
controller driver need to have the channel related structs
and variables as per the number of channels supported by IP.
Following changes are made to enable 64 Read / 64 Write
channel support:
o Defined HDMA specific macros to reflect the channel count.
o The count of ll_regions and dt_regions in dw_edma_chip and
dw_edma_pcie_data shall be in accordance to number of read
and write channels.
o In dw_edma_probe() configure the channels as per the channels
of the IP used.
o Changed mask types to u64 for higher channel counts.
Signed-off-by: Devendra K Verma <devendra.verma@amd.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260713064854.4065262-1-devverma@amd.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/dma/edma.h | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index 1fafd5b0e315..da7a5cc93ad4 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -14,6 +14,8 @@ #define EDMA_MAX_WR_CH 8 #define EDMA_MAX_RD_CH 8 +#define HDMA_MAX_WR_CH 64 +#define HDMA_MAX_RD_CH 64 struct dw_edma; @@ -89,12 +91,12 @@ struct dw_edma_chip { u16 ll_wr_cnt; u16 ll_rd_cnt; /* link list address */ - struct dw_edma_region ll_region_wr[EDMA_MAX_WR_CH]; - struct dw_edma_region ll_region_rd[EDMA_MAX_RD_CH]; + struct dw_edma_region ll_region_wr[HDMA_MAX_WR_CH]; + struct dw_edma_region ll_region_rd[HDMA_MAX_RD_CH]; /* data region */ - struct dw_edma_region dt_region_wr[EDMA_MAX_WR_CH]; - struct dw_edma_region dt_region_rd[EDMA_MAX_RD_CH]; + struct dw_edma_region dt_region_wr[HDMA_MAX_WR_CH]; + struct dw_edma_region dt_region_rd[HDMA_MAX_RD_CH]; /* interrupt emulation */ int db_irq; |