Merge branches 'clk-renesas', 'clk-thead', 'clk-mobileye', 'clk-amlogic' and 'clk-spacemit' into clk-next

* clk-renesas:
  clk: renesas: Add R-Car X5H CPG driver
  dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse Generator
  clk: r9a08g045: Add clocks and resets for CAN-FD
  dt-bindings: clock: renesas,versaclock7: Update maintainer
  clk: renesas: r9a09g047: Add LVDS clocks and resets
  clk: renesas: r9a09g077: Add LCDC and PLL3 clock support for RZ/T2H display pipeline
  clk: renesas: rzv2h-cpg: Extract PLL calculation helpers into shared library
  clk: renesas: rzv2h-cpg: Use per-SoC PLL reference frequency for calculations
  clk: renesas: r9a08g046: Add USB2.0 clock and reset entries
  clk: renesas: r9a09g077: Add RTC clocks
  clk: renesas: cpg-mssr: Implement dedicated MSTP delay logic for RZ/T2H LCDC and RTC
  clk: renesas: r9a08g046: Add clock and reset entries for GE3D
  clk: renesas: r9a08g046: Add clock and reset entries for SDHI
  clk: renesas: r9a09g047: Add audio clock and reset support
  dt-bindings: clock: renesas: Add audio clock inputs for RZ/V2H family
  dt-bindings: clock: renesas,r9a09g077/87: Add PCLKRTC clock ID
  dt-bindings: clock: renesas,r9a09g077/87: Add LCDC_CLKD clock ID

* clk-thead:
  clk: thead: allow COMPILE_TEST builds

* clk-mobileye:
  clk: eyeq: Add EyeQ7H compatibles
  clk: eyeq: Drop PLL, dividers, and fixed factors structs
  clk: eyeq: Convert clocks declaration to eqc_clock
  clk: eyeq: Introduce a generic clock type
  clk: eyeq: Prefix the PLL registers with the PLL type
  clk: fixed-factor: Export __clk_hw_register_fixed_factor()
  clk: fixed-factor: Rework initialization with parent clocks
  reset: eyeq: Add EyeQ7H compatibles
  dt-bindings: soc: mobileye: Add EyeQ7H OLB

* clk-amlogic:
  clk: amlogic: Add A9 peripherals clock controller driver
  dt-bindings: clock: Add Amlogic A9 peripherals clock controller
  clk: amlogic: Add A9 AO clock controller driver
  dt-bindings: clock: Add Amlogic A9 AO clock controller
  clk: meson: align gxbb_32k_clk_sel number of parents with actual count

* clk-spacemit:
  clk: spacemit: k3: fix missing /2 factor in i2s sysclk dividers
  clk: spacemit: k3: fix i2s clock topology
  dt-bindings: soc: spacemit: k3: add i2s_sysclk, i2s_bclk_factor and i2s1_sysclk_src IDs
  clk: spacemit: k3: Add UFS refclk clock
  dt-bindings: soc: spacemit: k3: Add clock ID for UFS refclk
  clk: spacemit: k3: fix parent clock of UFS aclk