diff options
| author | Matt Roper <matthew.d.roper@intel.com> | 2026-04-24 13:48:13 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2026-04-27 13:20:34 -0700 |
| commit | cdf9781025b3ed18f15f6c061c070b8bdcc1716f (patch) | |
| tree | f270be878bb013e2693a85011380edcc4f64307d /include/linux/timerqueue_types.h | |
| parent | 176f302e313a7e9038f878719dd0865045b5b2b6 (diff) | |
drm/xe: Stop programming BLIT_CCTL on Xe2 and later platforms
Xe1 platforms used the BLIT_CCTL register to specify the MOCS value that
would be used for BCS engine instructions that did not have a way of
specifying a MOCS index directly. From Xe2 onward, all BCS instructions
now have explicit instruction fields for specifying a MOCS index and the
BLIT_CCTL register is now a dummy register with no valid fields.
Although continuing to write to it today has no effect, the register
could repurposed in future platforms, so restrict the BLIT_CCTL RTP
entry to only apply to Xe1 platforms.
Bspec: 60280
Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com>
Link: https://patch.msgid.link/20260424-engine-setup-v2-3-59cc620a25f1@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Diffstat (limited to 'include/linux/timerqueue_types.h')
0 files changed, 0 insertions, 0 deletions
