diff options
| author | Alexey Charkov <alchark@flipper.net> | 2026-08-05 17:45:09 +0400 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2026-08-05 22:45:22 +0200 |
| commit | 586ff159ec02533c17dd928641529cb0b52e9c62 (patch) | |
| tree | 86c9404d120670afe00e8b00bc9943ea0a9a6364 /include/linux/timerqueue_types.h | |
| parent | b520d056f2619972ad09ced2985b534bba4f9599 (diff) | |
clk: rockchip: rk3576: fix source muxes for SPI0..SPI4
The TRM defines available source muxes for SPI0..SPI4 as
- b00: clk_gpll_div6_src
- b01: clk_gpll_div8_src
- b10: clk_cpll_div10_src
- b11: clk_xin_osc0_func
Which doesn't match what the current clock driver implements, making it
impossible to derive some SPI clock rates such as 37.125 MHz (which
requires clk_gpll_div8_src as the source mux).
Add a correct mux definition per TRM and point SPI0..SPI4 clocks at it.
Fixes: cc40f5baa91b ("clk: rockchip: Add clock controller for the RK3576")
Signed-off-by: Alexey Charkov <alchark@flipper.net>
Link: https://patch.msgid.link/20260805-rk3576-spi-clk-v1-1-2f040d0d163b@flipper.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'include/linux/timerqueue_types.h')
0 files changed, 0 insertions, 0 deletions