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authorQiuxu Zhuo <qiuxu.zhuo@intel.com>2026-07-30 10:42:31 +0800
committerTony Luck <tony.luck@intel.com>2026-07-30 11:30:58 -0700
commit540b79536f3a89a66c5b6c490110298d43025618 (patch)
tree8a0efc7f4a312622e0f19bee2dcc8f30b6ebae77 /include/linux/timerqueue_types.h
parentf4008169bd320eedb9ddf2b39eeb21370ddac278 (diff)
EDAC/igen6: Fix channel selection hash
In channel selection hash mode, the hardware decoding logic always includes the channel interleave bit in XOR operations. However, the hash mask may or may not include this channel interleave bit. When the mask does include this bit, the current igen6_edac code performs XOR on the interleave bit twice, effectively ignoring it - which is incorrect. Fix this issue by ensuring the hash mask always includes the interleave bit, so XOR is performed on the interleave bit exactly once. Fixes: 10590a9d4f23 ("EDAC/igen6: Add EDAC driver for Intel client SoCs using IBECC") Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20260730024238.4096623-4-qiuxu.zhuo@intel.com
Diffstat (limited to 'include/linux/timerqueue_types.h')
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