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authorMatt Roper <matthew.d.roper@intel.com>2026-04-08 15:27:44 -0700
committerMatt Roper <matthew.d.roper@intel.com>2026-04-13 12:54:49 -0700
commit1a2a722ff96749734a5585dfe7f0bea7719caa8b (patch)
tree404998217afd9f7a06e373aae2ee15dda6683c89 /include/linux/timerqueue_types.h
parentcd84bfbba7feb4c1e72356f14de026dfda1a9e2a (diff)
drm/xe/debugfs: Correct printing of register whitelist ranges
The register-save-restore debugfs prints whitelist entries as offset ranges. E.g., REG[0x39319c-0x39319f]: allow read access for a single dword-sized register. However the GENMASK value used to set the lower bits to '1' for the upper bound of the whitelist range incorrectly included one more bit than it should have, causing the whitelist ranges to sometimes appear twice as large as they really were. For example, REG[0x6210-0x6217]: allow rw access was also intended to be a single dword-sized register whitelist (with a range 0x6210-0x6213) but was printed incorrectly as a qword-sized range because one too many bits was flipped on. Similar 'off by one' logic was applied when printing 4-dword register ranges and 64-dword register ranges as well. Correct the GENMASK logic to print these ranges in debugfs correctly. No impact outside of correcting the misleading debugfs output. Fixes: d855d2246ea6 ("drm/xe: Print whitelist while applying") Reviewed-by: Stuart Summers <stuart.summers@intel.com> Link: https://patch.msgid.link/20260408-regsr_wl_range-v1-1-e9a28c8b4264@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Diffstat (limited to 'include/linux/timerqueue_types.h')
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