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| author | John Hubbard <jhubbard@nvidia.com> | 2026-06-01 20:20:54 -0700 |
|---|---|---|
| committer | Alexandre Courbot <acourbot@nvidia.com> | 2026-06-02 22:33:15 +0900 |
| commit | a5bf742bc28a4e064059c8d137970e56669a21a0 (patch) | |
| tree | 876a1afe837c140b36d1184d440ffdc8745c6c4b /include/linux/timerqueue.h | |
| parent | f66287cf155e47b604118ee1e7731ff634d8dbe9 (diff) | |
gpu: nova-core: Blackwell: use correct sysmem flush registers
Blackwell GPUs moved the sysmem flush page registers away from the
Ampere/Ada location. GB10x routes the flush through a pair of HSHUB0
register sets (primary and egress) that must both be programmed to
the same address. GB20x routes it through FBHUB0.
Define these registers relative to their HSHUB0 and FBHUB0 bases, as
Open RM does, and implement the flush paths in the GB10x and GB20x
framebuffer HALs.
Signed-off-by: John Hubbard <jhubbard@nvidia.com>
Reviewed-by: Eliot Courtney <ecourtney@nvidia.com>
Link: https://patch.msgid.link/20260602032111.224790-7-jhubbard@nvidia.com
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Diffstat (limited to 'include/linux/timerqueue.h')
0 files changed, 0 insertions, 0 deletions
