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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2026-03-30 11:44:45 +0100 |
|---|---|---|
| committer | Biju Das <biju.das.jz@bp.renesas.com> | 2026-04-16 06:54:09 +0100 |
| commit | 7cbba8a8ba0219a267844d3116dbc77cecb4fcf8 (patch) | |
| tree | d934b3aec649d5135f3c76bd1047f188795289d0 /include/linux/timerqueue.h | |
| parent | 5bfa858d53bb252d7a012c2e0a97ae18182edfb1 (diff) | |
drm: renesas: rzg2l_mipi_dsi: Increase reset deassertion delay
The RZ/G2L hardware manual (Rev. 1.50, May 2025), Section 34.4.2.1,
requires waiting at least 1 msec after deasserting the CMN_RSTB signal
before the DSI-Tx module is ready. Increase the delay from 1 usec to
1 msec by replacing udelay(1) with fsleep(1000) for RZ/G2L SoCs.
Fixes: 7a043f978ed1 ("drm: rcar-du: Add RZ/G2L DSI driver")
Cc: stable@vger.kernel.org
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Tested-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Link: https://patch.msgid.link/20260330104450.128512-3-biju.das.jz@bp.renesas.com
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Diffstat (limited to 'include/linux/timerqueue.h')
0 files changed, 0 insertions, 0 deletions