ASoC: rockchip: Reorder clock enable sequence

bui duc phuc <phucduc.bui@gmail.com> says:

This series reorders the runtime resume clock enable sequence in the
Rockchip SPDIF and PDM drivers to enable the bus clock before the
functional controller clock.

It also updates the SPDIF DT binding clock descriptions to match the
actual clock usage in the driver.

Additionally, this v2 adds two new patches addressing issues reported
by the Sashiko AI Review tool regarding regcache sync failure handling
and runtime PM resume status validation.

Testing:
  - Patch 1: Verified (dt_binding_check passed).
  - Patches 2 to 5: Compile tested only. Please help test if you have
    the relevant Rockchip hardware.

Link: https://patch.msgid.link/20260602101608.45137-1-phucduc.bui@gmail.com

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