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| author | Stephen Boyd <sboyd@kernel.org> | 2026-08-11 23:03:45 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2026-08-11 23:03:45 -0700 |
| commit | 1353d95e637b576e83ef0551d31a72002014cf88 (patch) | |
| tree | 86c9f9899a1e0623b22d33e353b4df13712f4e0e /include/linux/timerqueue.h | |
| parent | 8cdeaa50eae8dad34885515f62559ee83e7e8dda (diff) | |
| parent | 586ff159ec02533c17dd928641529cb0b52e9c62 (diff) | |
Merge tag 'v7.3-rockchip-clk1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull Rockchip clk driver updates from Heiko Stuebner:
- Clock driver for Rockchip RV1106
- Fix for Rockchip rk3576 spi source mux
- Better representing fractional PLL coefficients in Rockchip
clk driver
- Fix for the Rockchip dclk of the 3rd video-port to not affect
other compoents when its rate gets changed
* tag 'v7.3-rockchip-clk1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: rk3576: fix source muxes for SPI0..SPI4
clk: rockchip: Add clock controller for the RV1106
dt-bindings: clock: rockchip: Add RV1106 CRU support
clk: rockchip: Fractional PLL coefficient on RK3588/RK3576 is two's complement
clk: rockchip: Fix the fractional part denominator on RK3588/RK3576 PLLs
clk: rockchip: rk3588: Allow VP2 the same sourcing options as other VPs
clk: rockchip: rk3588: Don't change PLL rates when setting dclk_vop2_src
Diffstat (limited to 'include/linux/timerqueue.h')
0 files changed, 0 insertions, 0 deletions