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| author | Adrian Hunter <adrian.hunter@intel.com> | 2026-01-06 18:44:16 +0200 |
|---|---|---|
| committer | Alexandre Belloni <alexandre.belloni@bootlin.com> | 2026-01-14 15:53:34 +0100 |
| commit | 540a55a5bafd0ddbeb87672fe569c15954b47038 (patch) | |
| tree | 6797a2043c0a7c879944c6016069ee8f42cdf05d /include/linux/i2c/git@git.tavy.me:linux.git | |
| parent | 9b1679028e760259eaf817b8ceecad9b03a60118 (diff) | |
i3c: mipi-i3c-hci-pci: Define Multi-Bus instances for supported controllers
Define Multi-Bus Instances at offset 0x400 for Intel controllers.
Intel SoCs include two I3C PCI devices in the Low Power Subsystem (LPSS),
each capable of hosting two I3C buses. Panther Lake and Wildcat Lake
support three buses in total (IDs 0–2), while Nova Lake supports four
(IDs 0–3).
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260106164416.67074-12-adrian.hunter@intel.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Diffstat (limited to 'include/linux/i2c/git@git.tavy.me:linux.git')
0 files changed, 0 insertions, 0 deletions