diff options
| author | Gustavo Sousa <gustavo.sousa@intel.com> | 2026-05-14 18:44:44 -0300 |
|---|---|---|
| committer | Gustavo Sousa <gustavo.sousa@intel.com> | 2026-05-15 18:05:12 -0300 |
| commit | 8f765f0c054e0fb39980a76b4c899b027395929d (patch) | |
| tree | c2492e496c11cf0a57e45d6d73496ce4445c6cce /include/linux/debugobjects.h | |
| parent | ff1d386a8359746d9699ac30336e3b0684c68958 (diff) | |
drm/xe: Define CACHE_MODE_1 as MCR register
CACHE_MODE_1 is a MCR register for all platforms that currently use it
in the Xe driver. Use XE_REG_MCR() when defining it.
Fixes: 8cd7e9759766 ("drm/xe: Add missing DG2 lrc workarounds")
Fixes: ff063430caa8 ("drm/xe/mtl: Add some initial MTL workarounds")
Bspec: 66534, 67788
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20260514-rtp-mcr-check-v3-1-30dd47855fee@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Diffstat (limited to 'include/linux/debugobjects.h')
0 files changed, 0 insertions, 0 deletions