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authorYury Norov <ynorov@nvidia.com>2026-04-27 17:41:18 -0400
committerYury Norov <ynorov@nvidia.com>2026-05-20 11:18:10 -0400
commit2c3f0541b99c60ac079228627ea325317e7d8b2a (patch)
tree6d42e918d416a16763a816f039969da86bf88075 /include/linux/debugobjects.h
parent27fa82620cbaa89a7fc11ac3057701d598813e87 (diff)
bitfield: add FIELD_GET_SIGNED()
The bitfields are designed in assumption that fields contain unsigned integer values, thus extracting the values from the field implies zero-extending. Some drivers need to sign-extend their fields, and currently do it like: dc_re += sign_extend32(FIELD_GET(0xfff000, tmp), 11); dc_im += sign_extend32(FIELD_GET(0xfff, tmp), 11); It's error-prone because it relies on user to provide the correct index of the most significant bit and proper 32 vs 64 function flavor. Thus, introduce a FIELD_GET_SIGNED(). With the new API, the above snippet turns into the more convenient: dc_re += FIELD_GET_SIGNED(0xfff000, tmp); dc_im += FIELD_GET_SIGNED(0xfff, tmp); It compiles (on x86_64) into just a couple instructions: shl and sar. When the mask includes MSB, the '<< __builtin_clzll(mask)' part becomes a NOP, and the compiler only emits a single sar: long long foo(long long reg) { 10: f3 0f 1e fa endbr64 return FIELD_GET_SIGNED(GENMASK_ULL(63, 60), reg); 14: 48 89 f8 mov %rdi,%rax 17: 48 c1 f8 3c sar $0x3c,%rax } 32-bit code generation is equally well. On arm32: long long foo(long long reg) { return FIELD_GET_SIGNED(0x00f00000ULL, reg); } generates: foo(long long): lsls r1, r0, #8 asrs r0, r1, #28 asrs r1, r1, #31 bx lr Signed-off-by: Yury Norov <ynorov@nvidia.com>
Diffstat (limited to 'include/linux/debugobjects.h')
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