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authorLinus Torvalds <torvalds@linux-foundation.org>2026-04-05 11:29:07 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2026-04-05 11:29:07 -0700
commiteb3765aa711ff93664cd5ffcf0c2df02da2d9c26 (patch)
treeeed6a30457abd7c455c5319297a350039ccd581c /include/asm-sh/git@git.tavy.me:linux.git
parent1791c390149f56313c425e8add1fd15baf40afb8 (diff)
parent01cc50ea5167bb14117257ec084637abe9e5f691 (diff)
Merge tag 'mips-fixes_7.0_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS fixes from Thomas Bogendoerfer: - Fix TLB uniquification for systems with TLB not initialised by firmware - Fix allocation in TLB uniquification - Fix SiByte cache initialisation - Check uart parameters from firmware on Loongson64 systems - Fix clock id mismatch for Ralink SoCs - Fix GCC version check for __mutli3 workaround * tag 'mips-fixes_7.0_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: mips: mm: Allocate tlb_vpn array atomically MIPS: mm: Rewrite TLB uniquification for the hidden bit feature MIPS: mm: Suppress TLB uniquification on EHINV hardware MIPS: Always record SEGBITS in cpu_data.vmbits MIPS: Fix the GCC version check for `__multi3' workaround MIPS: SiByte: Bring back cache initialisation mips: ralink: update CPU clock index MIPS: Loongson64: env: Check UARTs passed by LEFI cautiously
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