diff options
| author | Fangyu Yu <fangyu.yu@linux.alibaba.com> | 2026-05-12 22:43:30 +0800 |
|---|---|---|
| committer | Joerg Roedel <joerg.roedel@amd.com> | 2026-05-15 07:33:17 +0200 |
| commit | e861aaea2f478d23e9ee05edd4fd403f40ac75fa (patch) | |
| tree | 3e44f0a289384e907613529cba6aa0da0c18fd2f /drivers | |
| parent | 6c21eb174c6c7aebdecaf5c39e3100e6beb35faa (diff) | |
iommupt: Fixup build warning by using BIT_ULL() for RISCVPT_NC/IO
Fix build warning on 32-bit configurations by using BIT_ULL() for
RISCVPT_NC and RISCVPT_IO.
Fixes: 6c21eb174c6c ("iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202605121350.wZxB51k0-lkp@intel.com/
Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/iommu/generic_pt/fmt/riscv.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/iommu/generic_pt/fmt/riscv.h b/drivers/iommu/generic_pt/fmt/riscv.h index 2648bb57953e..ae9a76514416 100644 --- a/drivers/iommu/generic_pt/fmt/riscv.h +++ b/drivers/iommu/generic_pt/fmt/riscv.h @@ -64,8 +64,8 @@ enum { RISCVPT_PPN64 = GENMASK_ULL(53, 10), RISCVPT_PPN64_64K = GENMASK_ULL(53, 14), RISCVPT_PBMT = GENMASK_ULL(62, 61), - RISCVPT_NC = BIT(61), - RISCVPT_IO = BIT(62), + RISCVPT_NC = BIT_ULL(61), + RISCVPT_IO = BIT_ULL(62), RISCVPT_N = BIT_ULL(63), /* Svnapot encodings for ppn[0] */ |