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authorVal Packett <val@packett.cool>2026-03-04 16:06:23 -0300
committerVinod Koul <vkoul@kernel.org>2026-05-19 15:40:48 +0530
commitf546912bcac6463a22c5825e27a7952f8b48c887 (patch)
tree993eed4d286bbe8fbd39a2eb160f0b861204edbc /Documentation/gpu/intel-display/git@git.tavy.me:linux.git
parentfd6cd05ceabdf67635a4cef5145f79d1217bf11b (diff)
phy: qcom: qmp-combo: Move pipe_clk on/off to common
Keep the USB pipe clock working when the phy is in DP-only mode, because the dwc controller still needs it for USB 2.0 over the same Type-C port. Tested with the BenQ RD280UA monitor which has a downstream-facing port for data passthrough that's manually switchable between USB 2 and 3, corresponding to 4-lane and 2-lane DP respectively. Note: the suspend/resume callbacks were already gating the enable/disable of this clock only on init_count and not usb_init_count! Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Val Packett <val@packett.cool> Link: https://patch.msgid.link/20260304190827.176988-1-val@packett.cool Signed-off-by: Vinod Koul <vkoul@kernel.org>
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