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authorCe Sun <cesun102@amd.com>2026-03-24 11:29:52 +0800
committerAlex Deucher <alexander.deucher@amd.com>2026-07-01 11:51:08 -0400
commitfe3ede5cdac00fe17a6fdee3e0447835c03a913e (patch)
tree7e515bfafb8e582605a4d0459ee8ae7f4964e1d8
parent2b3877b00aae569cf52e0a190031b4f2826cba1b (diff)
drm/amdgpu: retire legacy PMFW eeprom RAS bad page handling
retire legacy PMFW eeprom RAS bad page handling Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Ce Sun <cesun102@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c33
1 files changed, 2 insertions, 31 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
index 292d76021644..d28e8958b0ff 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
@@ -916,33 +916,6 @@ int amdgpu_ras_eeprom_update_record_num(struct amdgpu_ras_eeprom_control *contro
return ret;
}
-static int amdgpu_ras_smu_eeprom_append(struct amdgpu_ras_eeprom_control *control)
-{
- struct amdgpu_device *adev = to_amdgpu_device(control);
- struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
-
- if (!amdgpu_ras_smu_eeprom_supported(adev) || !con)
- return 0;
-
- control->ras_num_bad_pages = con->bad_page_num;
-
- if (amdgpu_bad_page_threshold != 0 &&
- control->ras_num_bad_pages > con->bad_page_cnt_threshold) {
- dev_warn(adev->dev,
- "Saved bad pages %d reaches threshold value %d\n",
- control->ras_num_bad_pages, con->bad_page_cnt_threshold);
-
- if (adev->cper.enabled && amdgpu_cper_generate_bp_threshold_record(adev))
- dev_warn(adev->dev, "fail to generate bad page threshold cper records\n");
-
- if ((amdgpu_bad_page_threshold != -1) &&
- (amdgpu_bad_page_threshold != -2))
- con->is_rma = true;
- }
-
- return 0;
-}
-
/**
* amdgpu_ras_eeprom_append -- append records to the EEPROM RAS table
* @control: pointer to control structure
@@ -961,15 +934,13 @@ int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control,
const u32 num)
{
struct amdgpu_device *adev = to_amdgpu_device(control);
+ struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
int res, i;
uint64_t nps = AMDGPU_NPS1_PARTITION_MODE;
- if (!__is_ras_eeprom_supported(adev))
+ if (!__is_ras_eeprom_supported(adev) || !con)
return 0;
- if (amdgpu_ras_smu_eeprom_supported(adev))
- return amdgpu_ras_smu_eeprom_append(control);
-
if (num == 0) {
dev_err(adev->dev, "will not append 0 records\n");
return -EINVAL;