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| author | Gerald Loacker <gerald.loacker@wolfvision.net> | 2026-07-25 18:56:04 +0200 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2026-08-06 21:35:36 +0530 |
| commit | f82ff8609f582ca5105e45f18dfc3e949dfeaef1 (patch) | |
| tree | 45a837117dfb065e2e9791bf9ec14ecf60751d0e | |
| parent | 4fae43e33a7c10951fbdc6baf409d51bd66aaefb (diff) | |
dt-bindings: phy: rockchip-inno-csi-dphy: add rockchip,clk-lane-phase property
Add support for the optional rockchip,clk-lane-phase device tree property
to allow board-specific tuning of the clock lane sampling phase for
improved signal integrity across supported data rates.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Michael Riesch <michael.riesch@collabora.com>
Signed-off-by: Gerald Loacker <gerald.loacker@wolfvision.net>
Link: https://patch.msgid.link/20260725-feature-mipi-csi-dphy-4k60-v4-2-5b2c4626d31e@wolfvision.net
Signed-off-by: Vinod Koul <vkoul@kernel.org>
| -rw-r--r-- | Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml index 03950b3cad08..913aa688c0ae 100644 --- a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml @@ -56,6 +56,16 @@ properties: description: Some additional phy settings are access through GRF regs. + rockchip,clk-lane-phase: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + default: 3 + description: + Clock lane sampling phase selection (hardware tap index 0–7). Each step + corresponds to an approximately 40 ps delay as described in the hardware + specification. + required: - compatible - reg |