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authorTaimur Hassan <Syed.Hassan@amd.com>2026-04-24 20:56:30 -0500
committerAlex Deucher <alexander.deucher@amd.com>2026-05-05 09:56:53 -0400
commitea3ffb7f4b79dfce5de131d18bfe276c8a9700aa (patch)
tree789462a213a4e9df6bee75f39dd764d1c9d7e492
parent706364231119bddb0aaa2c8e0fa662311ff9302e (diff)
drm/amd/display: Promote DC to 3.2.381
This version brings along following update: -add max bandwidth budget to QoS interface -Update tmz field for LSDMA -fix buffer overruns warnings -add memory bandwidth override debug interface -Find link encoder for flexible DIG mapping cases -Fix type mismatches using guards and explicit casts -Fix type mismatches in DC and DMUB modules -Skip HDR metadata update when Smart Power OLED enabled -Rename backlight_properties to pwr_backlight_properties -remove watermark range notify -Clean Up Legacy DML Content -Implement block sequencing infrastructure for modular hardware operations. -Do DML float narrowing explicit -Fix type mismatches in DML and normalize loop bounds -Remove unused state param from enable_link_analog -Fix Color Manager (3DLUT, Shaper, Blend) Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/display/dc/dc.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 757ec9aff0b2..9bd4b0bb47df 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -63,7 +63,7 @@ struct dcn_dsc_reg_state;
struct dcn_optc_reg_state;
struct dcn_dccg_reg_state;
-#define DC_VER "3.2.380"
+#define DC_VER "3.2.381"
/**
* MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC