diff options
| author | Stefano Radaelli <stefano.r@variscite.com> | 2026-06-08 16:41:08 +0200 |
|---|---|---|
| committer | Frank Li <Frank.Li@nxp.com> | 2026-06-29 15:16:36 -0400 |
| commit | dfee5fefc3ecd29794c79b3f5284d759cfdc869e (patch) | |
| tree | b20df7b96548e8751a09d53c0e633982e618fb54 | |
| parent | dd7858bbdfa84beddf7d08bb82eacc8010221493 (diff) | |
arm64: dts: imx8mp-var-som-symphony: add HDMI support
Enable the HDMI display pipeline and HDMI audio support on the Symphony
carrier board.
Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index 698f02fc39a5..0beaee5f81c9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -48,6 +48,18 @@ }; }; + native-hdmi-connector { + compatible = "hdmi-connector"; + label = "HDMI OUT"; + type = "a"; + + port { + hdmi_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + pcie0_refclk: pcie0-refclk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -74,6 +86,43 @@ states = <3300000 0x0 1800000 0x1>; vin-supply = <&ldo5>; }; + + sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + }; +}; + +&aud2htx { + status = "okay"; +}; + +&hdmi_pai { + status = "okay"; +}; + +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + status = "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status = "okay"; }; &i2c3 { @@ -152,6 +201,10 @@ }; }; +&lcdif3 { + status = "okay"; +}; + &pcie { reset-gpios = <&pcal6408 1 GPIO_ACTIVE_LOW>; status = "okay"; @@ -253,6 +306,15 @@ }; &iomuxc { + pinctrl_hdmi: hdmigrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x10 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 |