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| author | Stafford Horne <shorne@gmail.com> | 2026-05-22 16:49:51 +0100 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2026-05-23 06:00:52 +0100 |
| commit | cf40e2cee8fe86d54f7eeb38944366d5c23e42dc (patch) | |
| tree | 1e73a8ebf9e729f8b376ea8c5e1a228d8d375a7f | |
| parent | 431400d49cac4bac944fc2d989921003314667ae (diff) | |
openrisc: Cache invalidation cleanup
When working on new cache invalidation functions I noticed these
cleanups in the cache initialization code. Remove unused and commented
instructions to avoid confusion.
Signed-off-by: Stafford Horne <shorne@gmail.com>
| -rw-r--r-- | arch/openrisc/kernel/head.S | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/arch/openrisc/kernel/head.S b/arch/openrisc/kernel/head.S index bd760066f1cd..65f474c2df4f 100644 --- a/arch/openrisc/kernel/head.S +++ b/arch/openrisc/kernel/head.S @@ -852,26 +852,19 @@ _ic_enable: l.sll r14,r30,r28 /* Establish number of cache sets - r16 contains number of cache sets r28 contains log(# of cache sets) */ l.andi r26,r24,SPR_ICCFGR_NCS l.srli r28,r26,3 - l.ori r30,r0,1 - l.sll r16,r30,r28 /* Invalidate IC */ l.addi r6,r0,0 l.sll r5,r14,r28 -// l.mul r5,r14,r16 -// l.trap 1 -// l.addi r5,r0,IC_SIZE 1: l.mtspr r0,r6,SPR_ICBIR l.sfne r6,r5 l.bf 1b l.add r6,r6,r14 - // l.addi r6,r6,IC_LINE /* Enable IC */ l.mfspr r6,r0,SPR_SR @@ -918,13 +911,10 @@ _dc_enable: l.sll r14,r30,r28 /* Establish number of cache sets - r16 contains number of cache sets r28 contains log(# of cache sets) */ l.andi r26,r24,SPR_DCCFGR_NCS l.srli r28,r26,3 - l.ori r30,r0,1 - l.sll r16,r30,r28 /* Invalidate DC */ l.addi r6,r0,0 |