diff options
| author | Biju Das <biju.das.jz@bp.renesas.com> | 2026-03-24 11:43:11 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-03-26 19:40:20 +0100 |
| commit | bf497e7babb5d14570b18b5d2c8a6bb14d4a733b (patch) | |
| tree | 266cfbccad119369c77708095989da52f0bc8a49 | |
| parent | fa3e973ca2d7a46b9f4ad5611b42d1885d7a77b6 (diff) | |
clk: renesas: rzg2l: Re-enable critical module clocks during resume
After a suspend/resume cycle, critical module clocks (CLK_IS_CRITICAL)
may be left disabled as there is no owning driver to restore them,
unlike regular clocks.
Add rzg2l_mod_enable_crit_clock_init_mstop() which walks all module
clocks on resume, re-enables any critical clock found disabled, and then
restores the MSTOP state for clocks that have one via the existing
helper. This replaces the direct call to rzg2l_mod_clock_init_mstop()
in rzg2l_cpg_resume(), preserving the correct clock-before-MSTOP restore
ordering.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260324114329.268249-7-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | drivers/clk/renesas/rzg2l-cpg.c | 21 |
1 files changed, 18 insertions, 3 deletions
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 738a4b182f27..70228d8a2ef3 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1599,8 +1599,8 @@ static void rzg2l_mod_clock_init_mstop_helper(struct rzg2l_cpg_priv *priv, { /* * Out of reset all modules are enabled. Set module state in case - * associated clocks are disabled at probe. Otherwise module is in - * invalid HW state. + * associated clocks are disabled at probe/resume. Otherwise module + * is in invalid HW state. */ scoped_guard(spinlock_irqsave, &priv->rmw_lock) { if (!rzg2l_mod_clock_is_enabled(&clk->hw)) @@ -1608,6 +1608,21 @@ static void rzg2l_mod_clock_init_mstop_helper(struct rzg2l_cpg_priv *priv, } } +static void rzg2l_mod_enable_crit_clock_init_mstop(struct rzg2l_cpg_priv *priv) +{ + struct mod_clock *clk; + struct clk_hw *hw; + + for_each_mod_clock(clk, hw, priv) { + if ((clk_hw_get_flags(&clk->hw) & CLK_IS_CRITICAL) && + (!rzg2l_mod_clock_is_enabled(&clk->hw))) + rzg2l_mod_clock_endisable_helper(&clk->hw, true, false); + + if (clk->mstop) + rzg2l_mod_clock_init_mstop_helper(priv, clk); + } +} + static void rzg2l_mod_clock_init_mstop(struct rzg2l_cpg_priv *priv) { struct mod_clock *clk; @@ -2103,7 +2118,7 @@ static int rzg2l_cpg_resume(struct device *dev) if (ret) return ret; - rzg2l_mod_clock_init_mstop(priv); + rzg2l_mod_enable_crit_clock_init_mstop(priv); return 0; } |