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authorChen-Yu Tsai <wenst@chromium.org>2026-02-24 15:03:05 +0800
committerAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>2026-02-24 10:27:32 +0100
commitbeb60276eb3a488d8154fc498ed11270bcfe979f (patch)
tree98f1dc73f5b0aaa3f3f0a639ca431d27024291d2
parent6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f (diff)
arm64: dts: mediatek: mt8195-cherry: Disable xhci1 completely
There is nothing connected to xhci1 in this design, nor in the actual end devices. Disable xhci1. Keep the USB PHY enabled, as it is a shared PHY and used for pcie1. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-rw-r--r--arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi11
1 files changed, 1 insertions, 10 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index b3761b80cac7..6e99122c65ac 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -1495,6 +1495,7 @@
};
&u3phy1 {
+ /* shared between xhci1 and pcie1. */
status = "okay";
};
@@ -1563,16 +1564,6 @@
vbus-supply = <&usb_vbus>;
};
-&xhci1 {
- status = "okay";
-
- phys = <&u2port1 PHY_TYPE_USB2>;
- rx-fifo-depth = <3072>;
- vusb33-supply = <&mt6359_vusb_ldo_reg>;
- vbus-supply = <&usb_vbus>;
- mediatek,u3p-dis-msk = <1>;
-};
-
&xhci2 {
status = "okay";
vbus-supply = <&usb_vbus>;