diff options
| author | Ankit Nautiyal <ankit.k.nautiyal@intel.com> | 2026-07-22 11:54:49 +0530 |
|---|---|---|
| committer | Ankit Nautiyal <ankit.k.nautiyal@intel.com> | 2026-07-22 12:39:01 +0530 |
| commit | b201029ca6956e18a6762fc955d1f497030ff912 (patch) | |
| tree | ecd28096b8241ab433113eff88aee31df6aff578 | |
| parent | d87992672c342e70e250c57f05a60cd70baff298 (diff) | |
drm/i915/display: Ensure a non-zero safe window from PTL onwards
From PTL onwards, the set context latency can be in the vactive region,
letting the safe window start some lines before the vblank start. The DSB
waits on this safe window instead of vblank (bits [15:14] select the safe
window signal from the DPT unit to start the DMA engine).
With modes that have a smaller vblank region, the computed guardband is
clamped to the vblank length, making the undelayed and delayed vblank
coincide. If the SCL is also 0, the 'safe window' becomes effectively 0,
and the DSB configured to wait for it gets stalled, since the hardware
never signals the safe window, leading to:
*ERROR* [CRTC:159:pipe A] flip_done timed out
*ERROR* [CRTC:159:pipe A] DSB 0 timed out waiting for idle
Keep the set context latency at a minimum of 1 to avoid this.
v2: Fix the bit numbers and correct the commit message. (Chaitanya)
Fixes: 4a68c7516c57 ("drm/i915/dsb: Use safe window path when VRR TG is used")
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Assisted-by: GitHub-Copilot:Claude-Opus-4.8
Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Link: https://patch.msgid.link/20260722062449.1166411-1-ankit.k.nautiyal@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 2c55a4818ad7..9dfd095f325f 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2486,6 +2486,19 @@ static int intel_crtc_set_context_latency(struct intel_crtc_state *crtc_state) set_context_latency = max(set_context_latency, intel_psr_min_set_context_latency(crtc_state)); + /* + * From PTL onwards, the set context latency can be in the vactive + * region, letting the safe window start some lines before the vblank + * start. With modes that have a smaller vblank region, the computed + * guardband is clamped to the vblank length, making the undelayed and + * delayed vblank coincide. If the SCL is also 0, the 'safe window' + * becomes effectively 0, and the DSB configured to wait for it gets + * stalled, since the hardware never signals the safe window. Keep the + * set context latency at a minimum of 1 to avoid this. + */ + if (DISPLAY_VER(display) >= 30) + set_context_latency = max(1, set_context_latency); + return set_context_latency; } |