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authorJoe Sandom <jsandom@axon.com>2026-04-20 10:13:14 +0100
committerBjorn Andersson <andersson@kernel.org>2026-07-02 14:31:23 -0500
commita23536d85805e455cbb6b101f05e48ab672edf9d (patch)
tree48b2909e50675b2bfb878c5e31a104f3195cb626
parent347318325974e888dc18d9fd15dcc48f671886c9 (diff)
arm64: dts: qcom: sm8550: add PCIe port labels
Add labels to the root port nodes (pcie0_port0, pcie1_port0) to allow board DTS files to reference them for adding endpoint devices to each pcie root port. Update the pcieport0 reference to pcie0_port0 in sm8550-hdk.dts and sm8550-qrd.dts to match the label rename in sm8550.dtsi. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Joe Sandom <jsandom@axon.com> Link: https://lore.kernel.org/r/20260420-rb5gen2-dts-v4-2-b461909c2de8@axon.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-rw-r--r--arch/arm64/boot/dts/qcom/sm8550-hdk.dts2
-rw-r--r--arch/arm64/boot/dts/qcom/sm8550-qrd.dts2
-rw-r--r--arch/arm64/boot/dts/qcom/sm8550.dtsi4
3 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
index ee13e6136a82..e821b731bdc4 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
@@ -1012,7 +1012,7 @@
status = "okay";
};
-&pcieport0 {
+&pcie0_port0 {
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
index 2fb2e0be5e4c..cf63109ff7bf 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
@@ -912,7 +912,7 @@
status = "okay";
};
-&pcieport0 {
+&pcie0_port0 {
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 1f2cafb1c380..aee4947fe70e 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -2455,7 +2455,7 @@
};
};
- pcieport0: pcie@0 {
+ pcie0_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -2657,7 +2657,7 @@
};
};
- pcie@0 {
+ pcie1_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;