diff options
| author | Ankit Nautiyal <ankit.k.nautiyal@intel.com> | 2026-02-04 10:32:47 +0530 |
|---|---|---|
| committer | Ankit Nautiyal <ankit.k.nautiyal@intel.com> | 2026-02-05 14:20:28 +0530 |
| commit | 79ee2fbb8e11ec193326ba3595aaabb46f96defc (patch) | |
| tree | 8391581f6d5da007536b1285fd3f2c07cf96a8ba | |
| parent | 32c471e8f0958fae3d461f4dd299090fa44a6d45 (diff) | |
drm/i915/alpm: Allow LOBF only if window1 > alpm check_entry lines
LOBF must be disabled if the number of lines within Window 1 is not greater
than ALPM_CTL[ALPM Entry Check]
v2: Consider the case where SCL is in the active region. (Ville)
Bspec:71041
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
Link: https://patch.msgid.link/20260204050250.762718-3-ankit.k.nautiyal@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_alpm.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c index 055184a3c7d5..27b26e5813dc 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.c +++ b/drivers/gpu/drm/i915/display/intel_alpm.c @@ -270,6 +270,23 @@ int intel_alpm_lobf_min_guardband(struct intel_crtc_state *crtc_state) return first_sdp_position + waketime_in_lines + crtc_state->set_context_latency; } +static bool intel_alpm_lobf_is_window1_sufficient(struct intel_crtc_state *crtc_state) +{ + struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + int vblank = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay; + int window1; + + /* + * LOBF must be disabled if the number of lines within Window 1 is not + * greater than ALPM_CTL[ALPM Entry Check] + */ + window1 = vblank - min(vblank, + crtc_state->vrr.guardband + + crtc_state->set_context_latency); + + return window1 > crtc_state->alpm_state.check_entry_lines; +} + void intel_alpm_lobf_compute_config_late(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state) { @@ -279,6 +296,11 @@ void intel_alpm_lobf_compute_config_late(struct intel_dp *intel_dp, if (!crtc_state->has_lobf) return; + if (!intel_alpm_lobf_is_window1_sufficient(crtc_state)) { + crtc_state->has_lobf = false; + return; + } + /* * LOBF can only be enabled if the time from the start of the SCL+Guardband * window to the position of the first SDP is greater than the time it takes |