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authorAndy Yan <andy.yan@rock-chips.com>2026-02-06 09:04:15 +0800
committerHeiko Stuebner <heiko@sntech.de>2026-02-22 23:28:48 +0100
commit753ed4fa4e815669a025e08f5101ce0d91f46c8a (patch)
treefb36f3434e74287372c71bfb390ae595629769d1
parent6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f (diff)
arm64: dts: rockchip: Add DisplayPort dt node for rk3576
The DisplayPort on rk3576 is compliant with DisplayPort Specification Version 1.4 with MST support, and share the USBDP combo PHY with USB 3.1 OTG0 controller. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Tested-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://patch.msgid.link/20260206010421.443605-6-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3576.dtsi28
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index 49ccdf12ef7e..53ff6bd027af 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1483,6 +1483,34 @@
};
};
+ dp: dp@27e40000 {
+ compatible = "rockchip,rk3576-dp";
+ reg = <0x0 0x27e40000 0x0 0x30000>;
+ interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&cru CLK_AUX16MHZ_0>;
+ assigned-clock-rates = <16000000>;
+ clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16MHZ_0>,
+ <&cru ACLK_DP0>;
+ clock-names = "apb", "aux", "hdcp";
+ resets = <&cru SRST_DP0>;
+ phys = <&usbdp_phy PHY_TYPE_DP>;
+ power-domains = <&power RK3576_PD_VO1>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dp0_in: port@0 {
+ reg = <0>;
+ };
+
+ dp0_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
sai7: sai@27ed0000 {
compatible = "rockchip,rk3576-sai";
reg = <0x0 0x27ed0000 0x0 0x1000>;