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authorGangliang Xie <ganglxie@amd.com>2026-03-17 15:31:48 +0800
committerAlex Deucher <alexander.deucher@amd.com>2026-03-30 14:37:27 -0400
commit5c36fd7fc6a84f36bebbef72fe29bec0682a6589 (patch)
tree7464eccdb3065d53022a4caa03e8a336a930ae11
parent27f5ff9e4a4150d7cf8b4085aedd3b77ddcc5d08 (diff)
drm/amdgpu: reset ras eeprom table when it is invalid
reset ras eeprom table when it is invalid Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
index 44fba4b6aa92..cdf4909592d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
@@ -1558,6 +1558,8 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 };
struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
+ int dev_var = adev->pdev->device & 0xF;
+ uint32_t vram_type = adev->gmc.vram_type;
int res;
if (amdgpu_ras_smu_eeprom_supported(adev))
@@ -1597,6 +1599,12 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
return amdgpu_ras_eeprom_reset_table(control);
}
+ if (!(adev->flags & AMD_IS_APU) && (dev_var == 0x5) &&
+ (vram_type == AMDGPU_VRAM_TYPE_HBM3E) &&
+ (hdr->version < RAS_TABLE_VER_V3)) {
+ return amdgpu_ras_eeprom_reset_table(control);
+ }
+
switch (hdr->version) {
case RAS_TABLE_VER_V2_1:
case RAS_TABLE_VER_V3: