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authorLuca Leonardo Scorcia <l.scorcia@gmail.com>2026-05-31 17:23:32 +0100
committerLinus Walleij <linusw@kernel.org>2026-06-08 23:55:43 +0200
commit439bc91d20188901dac698bed4921caac76d9074 (patch)
treee34f2687c91f8028cd06541299164ef9a4fb36f7
parent1c3044cab23a056ea28da47da1cdd667a39df0b8 (diff)
pinctrl: mediatek: mt8167: Fix Schmitt trigger register offset of pins 34-39
The correct Schmitt trigger register offset for pins 34-39 is 0xA00. Value was verified with SoC data sheet. Signed-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com> Fixes: 82d70627e94a ("pinctrl: mediatek: Add MT8167 Pinctrl driver") Signed-off-by: Linus Walleij <linusw@kernel.org>
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mt8167.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8167.c b/drivers/pinctrl/mediatek/pinctrl-mt8167.c
index 143c26622272..c812d614e9d4 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8167.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8167.c
@@ -244,7 +244,7 @@ static const struct mtk_pin_ies_smt_set mt8167_smt_set[] = {
MTK_PIN_IES_SMT_SPEC(24, 25, 0xA00, 12),
MTK_PIN_IES_SMT_SPEC(26, 30, 0xA00, 0),
MTK_PIN_IES_SMT_SPEC(31, 33, 0xA00, 1),
- MTK_PIN_IES_SMT_SPEC(34, 39, 0xA900, 2),
+ MTK_PIN_IES_SMT_SPEC(34, 39, 0xA00, 2),
MTK_PIN_IES_SMT_SPEC(40, 40, 0xA10, 11),
MTK_PIN_IES_SMT_SPEC(41, 43, 0xA00, 10),
MTK_PIN_IES_SMT_SPEC(44, 47, 0xA00, 11),