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authorPeng Yang <pyangyyd@gmail.com>2026-06-08 17:58:49 +0800
committerMark Brown <broonie@kernel.org>2026-06-10 00:07:39 +0100
commit3c60184e39b57e5efe664fe8540cdbc1bc7ea899 (patch)
tree9f1e83fec35e132bd02065e5b1edaf4085b7fa93
parent5ac5ec84734fd338867055d4d7b650f18a023cb0 (diff)
spi: dw: fix race between IRQ handler and error handler on SMP
On SMP systems, dw_spi_handle_err() can be called from the SPI core kthread while the IRQ handler is still accessing the FIFO on another CPU. Resetting the chip via dw_spi_reset_chip() during an active FIFO read/write causes a bus error. Fix this by calling disable_irq() before the chip reset, which masks the IRQ and waits for any in-flight handler to complete via synchronize_irq(). This ensures no handler is accessing the FIFO when the reset occurs. Signed-off-by: Peng Yang <pyangyyd@amazon.com> Suggested-by: Jonathan Chocron <jonnyc@amazon.com> Link: https://patch.msgid.link/20260608095849.3446-1-pyangyyd@amazon.com Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--drivers/spi/spi-dw-core.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
index b47637888c5c..4672bc2a873a 100644
--- a/drivers/spi/spi-dw-core.c
+++ b/drivers/spi/spi-dw-core.c
@@ -472,7 +472,9 @@ static inline void dw_spi_abort(struct spi_controller *ctlr)
if (dws->dma_mapped)
dws->dma_ops->dma_stop(dws);
+ disable_irq(dws->irq);
dw_spi_reset_chip(dws);
+ enable_irq(dws->irq);
}
static void dw_spi_handle_err(struct spi_controller *ctlr,