diff options
| author | Vivian Wang <wangruikang@iscas.ac.cn> | 2026-03-03 13:29:49 +0800 |
|---|---|---|
| committer | Paul Walmsley <pjw@kernel.org> | 2026-06-06 23:48:15 -0600 |
| commit | 1b2c6b56a9fa0dcbef461039937de22b1cbecc7d (patch) | |
| tree | b02abbf2d0059111b09d01fd34dace24d7c38fc6 | |
| parent | 26c171fc48539ac88d3697792b1fde9334af836c (diff) | |
riscv: mm: Unconditionally sfence.vma for spurious fault
Svvptc does not guarantee that it's safe to just return here. Since we
have already cleared our bit, if, theoretically, the bounded timeframe
for the accessed page to become valid still hasn't happened after sret,
we could fault again and actually crash.
Hopefully, these spurious faults should be rare enough that this is an
acceptable slowdown.
Cc: stable@vger.kernel.org
Fixes: 503638e0babf ("riscv: Stop emitting preventive sfence.vma for new vmalloc mappings")
Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>
Link: https://patch.msgid.link/20260303-handle-kfence-protect-spurious-fault-v2-5-f80d8354d79d@iscas.ac.cn
Signed-off-by: Paul Walmsley <pjw@kernel.org>
| -rw-r--r-- | arch/riscv/kernel/entry.S | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index ebf6918b4e9b..c6988983cdf7 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -75,8 +75,11 @@ /* Atomically reset the current cpu bit in new_valid_map_cpus */ amoxor.d a0, a1, (a0) - /* Only emit a sfence.vma if the uarch caches invalid entries */ - ALTERNATIVE("sfence.vma", "nop", 0, RISCV_ISA_EXT_SVVPTC, 1) + /* + * A sfence.vma is required here. Even if we had Svvptc, there's no + * guarantee that after returning we wouldn't just fault again. + */ + sfence.vma REG_L a0, TASK_TI_A0(tp) REG_L a1, TASK_TI_A1(tp) |